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UPD784938 Datasheet(PDF) 19 Page - NEC |
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UPD784938 Datasheet(HTML) 19 Page - NEC |
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19 / 733 page  19 Preliminary User’s Manual U13987EJ1V0UM00 CHAPTER 20 IEBus CONTROLLER ..................................................................................................... 467 20.1 IEBus Controller Function ...................................................................................................... 467 20.1.1 Communication protocol of IEBus ............................................................................................... 467 20.1.2 Determination of bus mastership (arbitration) ............................................................................ 468 20.1.3 Communication mode .................................................................................................................. 468 20.1.4 Communication address .............................................................................................................. 468 20.1.5 Broadcasting communication ...................................................................................................... 469 20.1.6 Transmission format of IEBus ..................................................................................................... 469 20.1.7 Transmit data ............................................................................................................................... 477 20.1.8 Bit format ...................................................................................................................................... 479 20.2 Simple IEBus Controller ......................................................................................................... 480 20.3 IEBus Controller Configuration ............................................................................................. 481 20.4 Internal Registers of IEBus Controller ................................................................................. 483 20.4.1 Internal register list ...................................................................................................................... 483 20.4.2 Description of internal registers .................................................................................................. 484 20.5 Interrupt Operations of IEBus Controller ............................................................................. 500 20.5.1 Interrupt control block .................................................................................................................. 500 20.5.2 Interrupt source list ...................................................................................................................... 501 20.6 Interrupt Generation Timing and Main CPU Processing .................................................... 502 20.6.1 Master transmission ..................................................................................................................... 502 20.6.2 Master reception .......................................................................................................................... 504 20.6.3 Slave transmission ....................................................................................................................... 505 20.6.4 Slave reception ............................................................................................................................ 506 20.6.5 Interval of occurrence of interrupt for IEBus control .................................................................. 507 20.7 Cautions when Using IEBus Controller ................................................................................ 510 CHAPTER 21 CLOCK OUTPUT FUNCTION ....................................................................................... 511 21.1 Configuration ............................................................................................................................ 511 21.2 Clock Output Mode Register (CLOM) ................................................................................... 513 21.3 Operation .................................................................................................................................. 514 21.3.1 Clock output ................................................................................................................................. 514 21.3.2 1-bit output port ............................................................................................................................ 515 21.3.3 Operation in standby mode ......................................................................................................... 515 21.4 Cautions .................................................................................................................................... 515 CHAPTER 22 EDGE DETECTION FUNCTION ................................................................................... 517 22.1 Edge Detection Function Control Registers ........................................................................ 517 22.1.1 External interrupt mode registers (INTM0, INTM1) .................................................................... 517 22.1.2 Sampling clock selection register (SCS0) .................................................................................. 520 22.2 Edge Detection for Pins P20, P25, and P26 ......................................................................... 521 22.3 P21 Pin Edge Detection .......................................................................................................... 522 22.4 Pin Edge Detection for Pins P22 to P24 ............................................................................... 523 22.5 Cautions .................................................................................................................................... 524 CHAPTER 23 INTERRUPT FUNCTIONS .............................................................................................. 525 23.1 Interrupt Request Sources ..................................................................................................... 526 23.1.1 Software interrupts ....................................................................................................................... 528 23.1.2 Operand error interrupts .............................................................................................................. 528 |
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