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UPD70F3201 Datasheet(PDF) 1 Page - NEC |
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UPD70F3201 Datasheet(HTML) 1 Page - NEC |
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1 / 98 page  MOS INTEGRATED CIRCUIT µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y V850ES/SA2 TM, V850ES/SA3TM 32-BIT SINGLE-CHIP MICROCONTROLLERS Document No. U15436EJ1V0PM00 (1st edition) Date Published June 2001 N CP(K) Printed in Japan PRELIMINARY PRODUCT INFORMATION The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. © 2001 DESCRIPTION The µPD703201, 703201Y, 70F3201, and 70F3201Y (V850ES/SA2), µPD703204, 703204Y, 70F3204, and 70F3204Y (V850ES/SA3) are products in the V850 Family TM of 32-bit single-chip microcontrollers, and include peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, and a DMA controller. In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/SA2 and V850ES/SA3 include instructions suited to digital servo control applications such as multiplication instructions executed via a hardware multiplier, saturation instructions, and bit manipulation instructions. As a real-time control system, this device provides a high-level cost performance ideal for ultra-low-power DVC and portable audio applications. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. V850ES/SA2, V850ES/SA3 User’s Manual Hardware: To be prepared V850ES User’s Manual Architecture: To be prepared FEATURES Number of instructions: 83 Minimum instruction execution time: 59 ns (@ 17 MHz operation with main system clock (fXX)) 74 ns (@ 13.5 MHz operation with main system clock (fXX)) General-purpose registers: 32 bits × 32 registers Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions Memory space: 64 MB linear address space Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB = Total four blocks External bus interface: 16-bit data bus Address bus: Separate output enabled Internal memory Mask ROM: 256 KB ( µPD703201, 703201Y, 703204, 703204Y) Flash memory: 256 KB ( µPD70F3201, 70F3201Y, 70F3204, 70F3204Y) RAM: 16 KB Interrupts and exceptions Non-maskable interrupts: 2 sources Maskable interrupts: 38 sources ( µPD703201, 70F3201) 39 sources ( µPD703201Y, 70F3201Y) 39 sources ( µPD703204, 70F3204) 40 sources ( µPD703204Y, 70F3204Y) Software exceptions: 32 sources Exception trap: 1 source I/O lines Total: 82 (V850ES/SA2) 102 (V850ES/SA3) Timer/counters 16-bit timer: 2 channels 8-bit timer: 4 channels Real-time counter (for watch): 1 channel Watchdog timer: 1 channel |
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