UPD70F3201 datasheet(89/98 Pages) NEC

Part #	UPD70F3201

Description	32-BIT SINGLE-CHIP MICROCONTROLLERS

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Manufacturer	NEC [NEC]

Direct Link	http://www.nec.com/

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Preliminary Product Information U15436EJ1V0PM

89

µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y

I

2C Bus Mode (

µµµµPD703201Y, 703204Y, 70F3201Y, 70F3204Y only)

(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V)

Normal Mode

High-Speed Mode

Parameter

Symbol

MIN.

MAX.

MIN.

MAX.

Unit

SCL clock frequency

fCLK

0

100

0

400

kHz

Bus-free time (between

stop/start conditions)

tBUF

<103>

4.7

–

1.3

–

µs

Hold time

Note 1

tHD:STA

<104>

4.0

–

0.6

–

µs

SCL clock low-level width

tLOW

<105>

4.7

–

1.3

–

µs

SCL clock high-level width

tHIGH

<106>

4.0

–

0.6

–

µs

Setup time for start/restart

conditions

tSU:STA

<107>

4.7

–

0.6

–

µs

CBUS

compatible

master

5.0

–––

µs

Data hold

time

I

2C mode

tHD:DAT

<108>

0

Note 2

–

0

Note 2

0.9

Note 3

µs

Data setup time

tSU:DAT

<109>

250

–

100

Note 4

–

ns

SDA and SCL signal rise time

tR

<110>

–

1,000

20 + 0.1Cb

Note 5

300

ns

SDA and SCL signal fall time

tF

<111>

–

300

20 + 0.1Cb

Note 5

300

ns

Stop condition setup time

tSU:STO

<112>

4.0

–

0.6

–

µs

Pulse width with spike

suppressed by input filter

tSP

<113>

––

050

ns

Capacitance load of each bus

line

Cb

–

400

–

400

pF

Notes 1. At the start condition, the first clock pulse is generated after the hold time.

2. The system requires a minimum of 300 ns hold time internally for the SDA signal (at VIHmin.

. of SCL

signal) in order to occupy the undefined area at the falling edge of SCL.

3. If the system does not extend the SCL signal low hold time (tLOW), only the maximum data hold time (tHD:

DAT

) needs to be satisfied.

4. The high-speed-mode I

2C bus can be used in a normal-mode I2C bus system. In this case, set the high-

speed-mode I

2C bus so that it meets the following conditions.

• If the system does not extend the SCL signal's low state hold time:

tSU:DAT

≥ 250 ns

• If the system extends the SCL signal's low state hold time:

Transmit the following data bit to the SDA line prior to releasing the SCL line (tRmax. + tSU:DAT = 1,000

+ 250 = 1,250 ns: Normal mode I

2C bus specification).

5.

Cb: Total capacitance of one bus line (unit: pF)

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UPD70F3201 Datasheet(PDF) 89 Page - NEC

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