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UPD70F3201 Datasheet(PDF) 80 Page - NEC |
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UPD70F3201 Datasheet(HTML) 80 Page - NEC |
80 / 98 page Preliminary Product Information U15436EJ1V0PM 80 µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y (2) In separate bus mode (a) Read cycle (CLKOUT asynchronous): In separate bus mode (TA = –40 to +85 °°°°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Address setup time (to RD ↓)tSARD <52> 0.5T – 15 ns Address hold time (from RD ↑)tHARD <53> 2 ns RD low-level width tWRDL <54> (1.5 + n) T – 10 ns Data setup time (to RD ↑)tSISD <55> 20 ns Data hold time (from RD ↑)tHISD <56> 0 ns Data setup time (to address) tSAID <57> (2 + n) T – 25 ns tSRDWT1 <58> 0.5T – 20 ns WAIT setup time (to RD ↓) tSRDWT2 <59> (0.5 + n) T – 20 ns tHRDWT1 <60> 0.5T ns WAIT hold time (from RD ↓) tHRDWT2 <61> (0.5 + n) T ns tSAWT1 <62> T – 20 ns WAIT setup time (to address) tSAWT2 <63> (1 + n) T – 20 ns tHAWT1 <64> T ns WAIT hold time (from address) tHAWT2 <65> (1 + n) T ns Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency) 2. n: Number of wait clocks inserted in bus cycle The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from X1. (b) Read cycle (CLKOUT synchronous): In separate bus mode (TA = –40 to +85 °°°°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Delay time from CLKOUT ↑ to address, CS tDKSA <66> 0 19 ns Data input setup time (to CLKOUT ↑)tSISDK <67> 15 ns Data input hold time (from CLKOUT ↑)tHKISD <68> 5 ns Delay time from CLKOUT ↓↑ to RD tDKSR <69> 0 19 ns WAIT setup time (to CLKOUT ↑)tSWTK <70> 15 ns WAIT hold time (from CLKOUT ↑)tHKWT <71> 5 ns Remark The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from X1. |
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