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UPD70F3201 Datasheet(PDF) 76 Page - NEC |
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UPD70F3201 Datasheet(HTML) 76 Page - NEC |
76 / 98 page Preliminary Product Information U15436EJ1V0PM 76 µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y (b) CLKOUT synchronous: In multiplexed bus mode (TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Delay time from CLKOUT ↑ to address tDKA <39> 0 19 ns Delay time from CLKOUT ↑ to address float tFKA <40> –12 7 ns Delay time from CLKOUT ↓ to ASTB tDKST <41> –12 7 ns Delay time from CLKOUT ↑ to RD, WRm tDKRDWR <42> –5 14 ns Data input setup time (to CLKOUT ↑)tSIDK <43> 15 ns Data input hold time (from CLKOUT ↑)tHKID <44> 5 ns Data output delay time from CLKOUT ↑ tDKOD <45> 19 ns WAIT setup time (to CLKOUT ↓)tSWTK <46> 15 ns WAIT hold time (from CLKOUT ↓)tHKWT <47> 5 ns HLDRQ setup time (to CLKOUT ↓)tSHQK <48> 15 ns HLDRQ hold time (from CLKOUT ↓)tHKHQ <49> 5 ns Delay time from CLKOUT ↑ to bus float tDKF <50> 19 ns Delay time from CLKOUT ↑ to HLDAK tDKHA <51> 19 ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. |
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