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UPD70F3201 Datasheet(PDF) 75 Page - NEC

Part # UPD70F3201
Description  32-BIT SINGLE-CHIP MICROCONTROLLERS
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD70F3201 Datasheet(HTML) 75 Page - NEC

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Preliminary Product Information U15436EJ1V0PM
75
µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Bus Timing
(1) Multiplexed bus mode
(a) CLKOUT asynchronous: In multiplexed bus mode
(TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB
↓)tSAST
<11>
0.5T – 15
ns
Address hold time (from ASTB
↓)tHSTA
<12>
0.5T – 15
ns
Delay time from RD
↓ to address float
tFRDA
<13>
2
ns
Data input setup time from address
tSAID
<14>
(2 + n)T – 25
ns
Data input setup time from RD
tSRID
<15>
(1 + n)T – 25
ns
Delay time from ASTB
↓ to RD↓, WRm↓
tDSTRDWR
<16>
0.5T – 15
ns
Data input hold time (from RD
↑)tHRDID
<17>
0
ns
Address output time from RD
tDRDA
<18>
(1 + i)T – 15
ns
Delay time from RD, WRm
↑ to ASTB↑
tDRDWRST
<19>
0.5T – 15
ns
Delay time from RD
↑ to ASTB↓
tDRDST
<20>
(1.5 + i)T – 15
ns
RD, WRm low-level width
tWRDWRL
<21>
(1 + n)T – 15
ns
ASTB high-level width
tWSTH
<22>
T – 15
ns
Data output time from WRm
tDWROD
<23>
15
ns
Data output setup time (to WRm
↑)tSODWR
<24>
(1 + n)T – 20
ns
Data output hold time (from WRm
↑)tHWROD
<25>
T – 15
ns
tSAWT1
<26>
n
≥ 1
1.5T – 25
ns
WAIT setup time (to address)
tSAWT2
<27>
n
≥ 1
(1.5 + n)T – 25
ns
tHAWT1
<28>
n
≥ 1
(0.5 + n)T
ns
WAIT hold time (from address)
tHAWT2
<29>
n
≥ 1
(1.5 + n)T
ns
tSSTWT1
<30>
n
≥ 1T – 25
ns
WAIT setup time (to ASTB
↓)
tSSTWT2
<31>
n
≥ 1
(1 + n)T – 25
ns
tHSTWT1
<32>
n
≥ 1nT
ns
WAIT hold time (from ASTB
↓)
tHSTWT2
<33>
n
≥ 1
(1 + n)T
ns
HLDRQ high-level width
tWHQH
<34>
T + 10
ns
HLDAK low-level width
tWHAL
<35>
T – 15
ns
Delay time from HLDAK
↑ to bus output
tDHAC
<36>
–3ns
Delay time from HLDRQ
↓ to HLDAK↓
tDHQHA1
<37>
1.5T
(2n + 7.5)T + 25
ns
Delay time from HLDRQ
↑ to HLDAK↑
tDHQHA2
<38>
0.5T
1.5T + 25
ns
Remarks 1.
T = 1/fCPU (fCPU: CPU operation clock frequency)
2.
n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3.
m = 0, 1
4.
i: Number of idle states inserted after the read cycle (0 or 1).
5.
The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from
X1.


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