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UPD70F3201 Datasheet(PDF) 73 Page - NEC |
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UPD70F3201 Datasheet(HTML) 73 Page - NEC |
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73 / 98 page  Preliminary Product Information U15436EJ1V0PM 73 µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y Clock Timing (1) Operating conditions (TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.3 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit X1 input cycle 58.8 ns XT1 input cycle tCYX <1> 28.5 µs X1 input high-level width 26.4 ns XT1 input high-level width tWXH <2> 12.8 µs X1 input low-level width 26.4 ns XT1 input low-level width tWXL <3> 12.8 µs X1 input rise time tXR <4> 0.5 (tCYX – tWXH – tWXL) ns X1 input fall time tXF <5> 0.5 (tCYX – tWXH – tWXL) ns CLKOUT output cycle tCYK <6> 58.8 ns 16 µs CLKOUT high-level width tWKH <7> 0.5tCYK – 5ns CLKOUT low-level width tWKL <8> 0.5tCYK – 5ns CLKOUT rise time tKR <9> 5 ns CLKOUT fall time tKF <10> 5 ns Remark Ensure that the duty for the X1 and XT1 input waveforms is between 45% and 55%. (2) Operating conditions (TA = –40 to +85°C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit X1 input cycle T.B.D. ns XT1 input cycle tCYX <1> T.B.D. µs X1 input high-level width T.B.D. ns XT1 input high-level width tWXH <2> T.B.D. µs X1 input low-level width T.B.D. ns XT1 input low-level width tWXL <3> T.B.D. µs X1 input rise time tXR <4> T.B.D. ns X1 input fall time tXF <5> T.B.D. ns CLKOUT output cycle tCYK <6> T.B.D. T.B.D. CLKOUT high-level width tWKH <7> T.B.D. ns CLKOUT low-level width tWKL <8> T.B.D. ns CLKOUT rise time tKR <9> T.B.D. ns CLKOUT fall time tKF <10> T.B.D. ns Remark Ensure that the duty for the X1 and XT1 input waveforms is between 45% and 55%. |
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