 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPD70F3201 Datasheet(PDF) 62 Page - NEC |
|
|
|||||||||||||||||||||||||||||
UPD70F3201 Datasheet(HTML) 62 Page - NEC |
|
|
62 / 98 page  Preliminary Product Information U15436EJ1V0PM 62 µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y (6/6) Execution Clock Flags Mnemonic Operand Opcode Operation ir l CY OV S Z SAT SXB reg1 00000000101RRRRR GR[reg1] ←sign-extend (GR[reg1] (7 : 0)) 11 1 SXH reg1 00000000111RRRRR GR[reg1] ←sign-extend (GR[reg1] (15 : 0)) 11 1 TRAP vector 00000 1111 11iiiii 0000000100000000 EIPC ←PC+4 (Restored PC) EIPSW ←PSW ECR.EICC ←Interrupt Code PSW.EP ←1 PSW.ID ←1 PC ←00000040H (when vector is 00H to 0FH) 00000050H (when vector is 10H to 1FH) 33 3 TST reg1,reg2 rrrrr 0010 11RRRRR result ←GR[reg2] AND GR[reg1] 1 1 1 0 ×× bit#3,disp16[reg1] 11bbb111110RRRRR dddddddddddddddd adr ←GR[reg1]+sign-extend(disp16) Z flag ←Not (Load-memory-bit (adr,bit#3)) 3 Note3 3 Note3 3 Note3 × TST1 reg2, [reg1] rrrrr 1111 11RRRRR 0000000011100110 adr ←GR[reg1] Z flag ←Not (Load-memory-bit (adr,reg2)) 3 Note3 3 Note3 3 Note3 × XOR reg1,reg2 rrrrr 0010 01RRRRR GR[reg2] ←GR[reg2] XOR GR[reg1] 1 1 1 0 ×× XORI imm16,reg1,reg2 rrrrr 1101 01RRRRR iiiiiiiiiiiiiiii GR[reg2] ←GR[reg1] XOR zero-extend (imm16) 1 1 1 0 ×× ZXB reg1 00000000100RRRRR GR[reg1] ←zero-extend (GR[reg1] (7 : 0)) 1 1 1 ZXH reg1 00000000110RRRRR GR[reg1] ←zero-extend (GR[reg1] (15 : 0)) 1 1 1 Notes 1. dddddddd: Higher 8 bits of disp9. 2. 3 clocks if the final instruction includes the PSW write access. 3. If there is no wait state (3 + the number of read access wait states). 4. n is the total number of list X load registers. (According to the number of wait states. Also, if there are no wait states, n is the number of list X registers.) 5. RRRRR: Other than 00000. 6. The lower halfword data only is valid. 7. ddddddddddddddddddddd: The higher 21 bits of disp22. 8. ddddddddddddddd: The higher 15 bits of disp16. 9. According to the number of wait states (1 if there are no wait states). 10. b: Bit 0 of disp16. 11. According to the number of wait states (2 if there are no wait states). 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. r r r r r = regID specification RRRRR = reg2 specification 13. i i i i i : Lower 5 bits of imm9. I I I I : Lower 4 bits of imm9. 14. sp/imm: Specified by bits 19 and 20 of the sub-opcode. |
Similar Part No. - UPD70F3201 |
|
Similar Description - UPD70F3201 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
