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UPD70F3201 Datasheet(PDF) 61 Page - NEC

Part # UPD70F3201
Description  32-BIT SINGLE-CHIP MICROCONTROLLERS
Download  98 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD70F3201 Datasheet(HTML) 61 Page - NEC

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Preliminary Product Information U15436EJ1V0PM
61
µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(5/6)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
ir
l
CY OV
S
Z SAT
reg1,reg2
rrrrr 1111 11RRRRR
0000000011000000
GR[reg2]
←GR[reg2] logically shift left by GR[reg1]
1
1
1
×
0
××
SHL
imm5,reg2
r r r r r 0 1 0 1 1 0 iiiii
GR[reg2]
←GR[reg2] logically shift left
by zero-extend(imm5)
11
1
×
0
××
reg1,reg2
rrrrr 1111 11RRRRR
0000000010000000
GR[reg2]
←GR[reg2] logically shift right by GR[reg1]
1
1
1
×
0
××
SHR
imm5,reg2
r r r r r 0 1 0 1 0 0 iiiii
GR[reg2]
←GR[reg2] logically shift right
by zero-extend(imm5)
11
1
×
0
××
SLD.B
disp7[ep],reg2
r r rrr0 110d dddd dd
adr
←ep+zero-extend(disp7)
GR[reg2]
←sign-extend(Load-memory(adr,Byte))
11 Note9
SLD.BU
disp4[ep],reg2
r r rrr0 0001 10dd dd
Note 17
adr
←ep+zero-extend(disp4)
GR[reg2]
←zero-extend(Load-memory(adr,Byte))
11 Note9
SLD.H
disp8[ep],reg2
r r rrr1 000d dddd dd
Note 18
adr
←ep+zero-extend(disp8)
GR[reg2]
←sign-extend(Load-memory(adr,Half-
word))
11 Note9
SLD.HU
disp5[ep],reg2
r r r rr0 00 011 1d dd d
Notes 17, 19
adr
←ep+zero-extend(disp5)
GR[reg2]
←zero-extend(Load-memory(adr,Half-
word))
11 Note9
SLD.W
disp8[ep],reg2
r rr rr1 01 0dd dd dd 0
Note 20
adr
←ep+zero-extend(disp8)
GR[reg2]
←Load-memory(adr,Word)
11 Note9
SST.B
reg2,disp7[ep]
rr rrr0 111d dddd dd
adr
←ep+zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
11
1
SST.H
reg2,disp8[ep]
rr rrr1 001d dddd dd
Note 18
adr
←ep+zero-extend(disp8)
Store-memory(adr,GR[reg2],Half-word)
11
1
SST.W
reg2,disp8[ep]
r r r rr1 01 0dd dd dd 1
Note 20
adr
←ep+zero-extend(disp8)
Store-memory(adr,GR[reg2],Word)
11
1
ST.B
reg2,disp16[reg1]
rrrrr 1110 10RRRRR
dddddddddddddddd
adr
←GR[reg1]+sign-extend(disp16)
Store-memory(adr,GR[reg2],Byte)
11
1
ST.H
reg2,disp16[reg1]
rrrrr 1110 11RRRRR
ddddddddddddddd0
Note 8
adr
←GR[reg1]+sign-extend(disp16)
Store-memory (adr,GR[reg2], Half-word)
11
1
ST.W
reg2,disp16[reg1]
rrr rr 111 01 1RRRRR
ddddddddddddddd1
Note 8
adr
←GR[reg1]+sign-extend(disp16)
Store-memory (adr,GR[reg2], Word)
11
1
STSR
regID,reg2
rrrrr 1111 11RRRRR
0000000001000000
GR[reg2]
←SR[regID]
1
1
1
SUB
reg1,reg2
rrrrr 0011 01RRRRR
GR[reg2]
←GR[reg2]–GR[reg1]
1
1
1
××
××
SUBR
reg1,reg2
rrrrr 0011 00RRRRR
GR[reg2]
←GR[reg1]–GR[reg2]
1
1
1
××
××
SWITCH
reg1
00000000010RRRRR
adr
←(PC+2) + (GR [reg1] logically shift left by 1)
PC
←(PC+2) + (sign-extend
(Load-memory (adr,Half-word)))
logically shift left by 1
55
5


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