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UPD70F3201 Datasheet(PDF) 59 Page - NEC

Part # UPD70F3201
Description  32-BIT SINGLE-CHIP MICROCONTROLLERS
Download  98 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD70F3201 Datasheet(HTML) 59 Page - NEC

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Preliminary Product Information U15436EJ1V0PM
59
µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(3/6)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
ir
l
CY OV
S
Z SAT
LD.H
disp16[reg1],reg2
rrr rr 111 00 1RRRRR
ddddddddddddddd0
Note 8
adr
←GR[reg1]+sign-extend(disp16)
GR[reg2]
←sign-extend(Load-memory(adr,Half-
word))
11
Note
11
Other than regID = PSW
1
1
1
LDSR
reg2,regID
rrr rr 111 11 1RRRRR
0000000000100000
Note 12
SR[regID]
←GR[reg2]
regID = PSW
1
1
1
××
××
×
LD.HU
disp16[reg1],reg2
rrrrr 1111 11RRRRR
ddddddddddddddd1
Note 8
adr
←GR[reg1]+sign-exend(disp16)
GR[reg2]
←zero-extend(Load-memory(adr,half-word)
11
Note
11
LD.W
disp16[reg1],reg2
rrrrr 1110 01RRRRR
ddddddddddddddd1
Note 8
adr
←GR[reg1]+sign-exend(disp16)
GR[reg2]
←Load-memory(adr,Word)
11
Note
11
reg1,reg2
rrrrr 0000 00RRRRR
GR[reg2]
←GR[reg1]
1
1
1
imm5,reg2
r r r r r 0 1 0 0 0 0 iiiii
GR[reg2]
←sign-extend(imm5)
1
1
1
MOV
imm32,reg1
00000110001RRRRR
iiiiiii iiii iiiii
iiiiiii iiii iiiii
GR[reg1]
←imm32
2
2
2
MOVEA
imm16,reg1,reg2
rrrrr 1100 01RRRRR
iiiiiii iiii iiiii
GR[reg2]
←GR[reg1]+sign-extend(imm16)
1
1
1
MOVHI
imm16,reg1,reg2
rrrrr 1100 10RRRRR
iiiiiii iiii iiiii
GR[reg2]
←GR[reg1]+(imm16 ll 016)1
1
1
reg1,reg2,reg3
rrrrr 1111 11RRRRR
wwwww01000100000
GR[reg3] ll GR[reg2]
←GR[reg2]xGR[reg1]
1
4
5
MUL
imm9,reg2,reg3
r r r r r 1 1 1 1 1 1 iiiii
wwwww01001IIII 00
Note 13
GR[reg3] ll GR[reg2]
←GR[reg2]xsign-extend(imm9)
1
4
5
reg1,reg2
rrrrr 0001 11RRRRR
GR[reg2]
←GR[reg2]Note6xGR[reg1]Note6
11
2
MULH
imm5,reg2
r r r r r 0 1 0 1 1 1 iiiii
GR[reg2]
←GR[reg2]Note6xsign-extend(imm5)
1
1
2
MULHI
imm16,reg1,reg2
rrrrr 1101 11RRRRR
iiiiiii iiii iiiii
GR[reg2]
←GR[reg1]Note6ximm16
1
1
2
reg1,reg2,reg3
rrrrr 1111 11RRRRR
wwwww01000100010
GR[reg3] ll GR[reg2]
←GR[reg2]xGR[reg1]
1
4
5
MULU
imm9,reg2,reg3
r r r r r 1 1 1 1 1 1 iiiii
wwwww01001IIII 10
Note 13
GR[reg3] ll GR[reg2]
←GR[reg2]xzero-extend(imm9)
1
4
5
NOP
000 00 000 00 00 00 00
Pass at least one clock cycle doing nothing.
1
1
1
NOT
reg1,reg2
rrrrr 0000 01RRRRR
GR[reg2]
←NOT(GR[reg1])
1
1
1
0
××
bit#3,disp16[reg1]
01bbb111110RRRRR
dddddddddddddddd
adr
←GR[reg1]+sign-extend(disp16)
Z flag
←Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,Z flag)
3
Note3
3
Note3
3
Note3
×
NOT1
reg2,[reg1]
rrrrr 1111 11RRRRR
0000000011100010
adr
←GR[reg1]
Z flag
←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,Z flag)
3
Note3
3
Note3
3
Note3
×


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