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UPD70F3201 Datasheet(PDF) 57 Page - NEC |
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UPD70F3201 Datasheet(HTML) 57 Page - NEC |
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57 / 98 page  Preliminary Product Information U15436EJ1V0PM 57 µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y 19.2 Instruction Set (In Alphabetical Order) (1/6) Execution Clock Flags Mnemonic Operand Opcode Operation ir l CY OV S Z SAT reg1,reg2 rrrrr 0011 10RRRRR GR[reg2] ←GR[reg2]+GR[reg1] 1 1 1 ×× ×× ADD imm5,reg2 r r r r r 0 1 0 0 1 0 iiiii GR[reg2] ←GR[reg2]+sign-extend(imm5) 1 1 1 ×× ×× ADDI imm16,reg1,reg2 rrrrr 1100 00RRRRR iiiiiiiiiiii iiii GR[reg2] ←GR[reg1]+sign-extend(imm16) 1 1 1 ×× ×× AND reg1,reg2 rrrrr 0010 10RRRRR GR[reg2] ←GR[reg2]AND GR[reg1] 1 1 1 0 ×× ANDI imm16,reg1,reg2 rrrrr 1101 10RRRRR iiiiiiiiiiii iiii GR[reg2] ←GR[reg1]AND zero-extend(imm16) 1 1 1 0 0 × When conditions are satisfied 2 Note2 2 Note2 2 Note2 Bcond disp9 ddd dd 101 1d ddc ccc Note 1 if conditions are satisfied then PC ←PC+sign-extend(disp9) When conditions are not satisfied 11 1 BSH reg2,reg3 r r rrr1 1111 1000 00 wwwww01101000010 GR[reg3] ←GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) 11 1 × 0 ×× BSW reg2,reg3 r r rrr1 1111 1000 00 wwwww01101000000 GR[reg3] ←GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR [reg2] (23 : 16) ll GR[reg2] (31 : 24) 11 1 × 0 ×× CALLT imm6 0000001000iiiiii CTPC ←PC+2(return PC) CTPSW ←PSW adr ←CTBP+zero-extend(imm6 logically shift left by 1) PC ←CTBP+zero-extend(Load-memory(adr,Half-word)) 44 4 bit#3, disp16[reg1] 10bbb111110RRRRR dddddddddddddddd adr ←GR[reg1]+sign-extend(disp16) Z flag ←Not(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,0) 3 Note3 3 Note3 3 Note3 × CLR1 reg2,[reg1] rrrrr 1111 11RRRRR 0000000011100100 adr ←GR[reg1] Z flag ←Not(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,0) 3 Note3 3 Note3 3 Note3 × cccc,imm5,reg2,reg3 r r r r r 1 1 1 1 1 1 iiiii wwwww011000cccc0 if conditions are satisfied then GR[reg3] ←sign-extended(imm5) else GR[reg3] ←GR[reg2] 11 1 CMOV cccc,reg1,reg2,reg3 rrrrr 1111 11RRRR wwwww011001cccc0 if conditions are satisfied then GR[reg3] ←GR[reg1] else GR[reg3] ←GR[reg2] 11 1 reg1,reg2 rrrrr 0011 11RRRRR result ←GR[reg2]–GR[reg1] 1 1 1 ×× ×× CMP imm5,reg2 r r r r r 0 1 0 0 1 1 iiiii result ←GR[reg2]–sign-extend(imm5) 1 1 1 ×× ×× CTRET 0000011111100000 0000000101000100 PC ←CTPC PSW ←CTPSW 33 3 R R R R R DBRET 0000011111100000 0000000101000110 PC ←DBPC PSW ←DBPSW 33 3 R R R R R |
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