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UPD70F3201 Datasheet(PDF) 51 Page - NEC |
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UPD70F3201 Datasheet(HTML) 51 Page - NEC |
51 / 98 page ![]() Preliminary Product Information U15436EJ1V0PM 51 µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y 17. RESET FUNCTION When a low-level signal is input to the RESET pin or the watchdog timer overflows (WDTRES), a system reset is applied and the various on-chip hardware devices are reset to their initial states. When the RESET pin goes from low level to high level, or when the WDTRES signal is automatically canceled, the reset state is released. When reset is released via RESET pin input, the CPU starts execution of the program after securing the oscillation stabilization time (OSTS register reset value: 2 19/fXX). When reset is released by the WDTRES signal, the main clock oscillator does not stop and oscillation stabilization time is not inserted. The following figure shows the configuration of the reset function. RESET Count clock Reset controller Watchdog timer Stop Overflow Reset signal Interrupt function |
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Similar Description - UPD70F3201 |
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