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UPD70F3201 Datasheet(PDF) 45 Page - NEC |
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UPD70F3201 Datasheet(HTML) 45 Page - NEC |
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45 / 98 page  Preliminary Product Information U15436EJ1V0PM 45 µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y 12.3 I 2C Bus (I2C) ( µµµµPD703201Y, 703204Y, 70F3201Y, 70F3204Y) The I 2C bus has the following features. Two modes • Operation stop mode (used when serial transfers are not performed to enable a reduction in power consumption) • I2C bus mode (supporting multi masters) The following figure shows the configuration of the I 2C bus Internal bus IIC status register 0 (IICS) IIC control register (IICC) Slave address register (SVA) Noise eliminator Noise eliminator Match signal IIC shift register (IIC) SO latch IICE D Q SET CLEAR CL1, CL0 SDA SCL N-ch open drain output N-ch open drain output Data hold time correction circuit ACK detector Wake up controller ACK detector Stop condition detector Serial clock counter Interrupt request signal generator Serial clock controller Serial clock wait controller Prescaler INTIIC fxx TM4 output CLD IIC clock select register (IICCL) IIC function expansion register (IICX) Internal bus LREL WREL SPIE WTIM ACKE STT SPT MSTS ALD EXC COI TRC ACKD STD SPD Start condition detector DAD SMC DFC CL1 CL0 CLX Remark fXX: Main clock frequency |
Similar Part No. - UPD70F3201 |
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Similar Description - UPD70F3201 |
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