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UPD70F3201 Datasheet(PDF) 34 Page - NEC |
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UPD70F3201 Datasheet(HTML) 34 Page - NEC |
34 / 98 page ![]() Preliminary Product Information U15436EJ1V0PM 34 µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y 7. CLOCK GENERATION FUNCTION The clock generation function has the following features. Main clock oscillator • 2 to 17 MHz (@ VDD = 2.3 to 2.7 V operation) • 2 to 13.5 MHz (@ VDD = 2.2 to 2.7 V operation) Subclock oscillator • 32.768 kHz (@ VDD = 2.2 to 2.7 V operation) Internal system clock generation • 6 levels (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32) Peripheral clock generation Clock output function The following figure shows the configuration of the clock generation function. FRC bit MFRC bit CK2 to CK0 bits STOP mode Subclock oscillator Port CM WDT clock control Prescaler 1 Prescaler 2 IDLE control HALT control HALT mode CPU clock A/D converter RTC clock Peripheral clock WDT clock Internal system clock Prescaler 3 Main clock oscillator Main clock oscillator stop control XT1 XT2 CLKOUT X1 X2 IDLE mode fXX/32 fXX/16 fXX/8 fXX/4 fXX/2 fXX fCPU fCLK fXX to fXX/512 fX/26 to fX/29 fXT fXT fX fXX fXW Remark fX, fXX: Main clock frequency fXT: Subclock frequency fCPU: CPU clock frequency fCLK: Internal system clock frequency fXW: Watchdog timer clock frequency |
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