UPD70F3201 datasheet(25/98 Pages) NEC

Part #	UPD70F3201

Description	32-BIT SINGLE-CHIP MICROCONTROLLERS

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Manufacturer	NEC [NEC]

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Preliminary Product Information U15436EJ1V0PM

25

µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y

3. CPU FUNCTIONS

The CPU of the V850ES/SA2 and V850ES/SA3 is based on RISC architecture and executes most instructions in a

1-clock cycle by using a 5-stage pipeline.

The features of the CPU are as follows.

Minimum instruction execution time: 59 ns (@ 17 MHz operation with main system clock (fXX))

74 ns (@ 13.5 MHz operation with main system clock (fXX))

Address space: 64 MB linear

• Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB = Total four blocks

General-purpose registers: 32 bits

× 32

Internal 32-bit architecture

5-stage pipeline control

Multiplication/division instructions

Saturation operation instructions

1-clock 32-bit shift instruction

Load/store instructions with long/short format

Internal memory

• Mask ROM:

256 KB (

µPD703201, 703201Y, 703204, 703204Y)

Flash memory: 256 KB (

µPD70F3201, 70F3201Y, 70F3204, 70F3204Y)

• RAM: 16 KB

Four types of bit manipulation instructions

• SET1

• CLR1

• NOT1

• TST1

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