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UPD70F3201 Datasheet(PDF) 23 Page - NEC |
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UPD70F3201 Datasheet(HTML) 23 Page - NEC |
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23 / 98 page  Preliminary Product Information U15436EJ1V0PM 23 µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y (8) Real-time counter (for watch) This counter counts the reference time period (1 second) for watch counting by using the 32.768 kHz subclock or the main clock. At the same time, the real-time counter can also be used as an interval timer that uses the main clock as a source clock. This counter includes week, date, hour, minute, and second counters, and is capable of counting up to 4,095 weeks. (9) Watchdog timer This timer detects inadvertent program loops, system abnormalities, etc. It can also be used as an interval timer. When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow occurs. (10) Serial interface (SIO) The V850ES/SA2 and V850ES/SA3 incorporate three kinds of serial interfaces: asynchronous serial interfaces (UART0 and UART1), clocked serial interfaces (V850E/SA2: CSI0 to CSI3, V850ES/SA3: CSI0 to CSI4), and an I 2C bus interface (I2C). The V850ES/SA2 is capable of using up to 4 channels and the V850ES/SA3 is capable of using up to 5 channels simultaneously. Among these channels, one channel can be switched between UART and CSI, and other one channel can be switched between CSI and I 2C. For UART0 and UART1, data is transferred via the TXDO, TXD1, RXD0, and RXD1 pins. For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins. For CSI4, data is transferred via the SO4, SI4, and SCK4 pins (V850ES/SA3 only). For I 2C, data is transferred via the SDA and SCL pins. I 2C is incorporated in the µPD703201Y, 703204Y, 70F3201Y and 70F3204Y only. UART includes an on-chip dedicated baud rate generator. (11) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins for the V850ES/SA2 and 16 for the V850ES/SA3. Conversion is performed using the successive approximation method. (12) D/A converter A two-channel 8-bit resolution D/A converter is incorporated. This D/A converter uses the R string method. (13) DMA controller A 4-channel DMA controller is incorporated. Data is transferred between internal RAM, on-chip peripheral I/O, and external memory based on interrupt requests by the on-chip peripheral I/O. (14) ROM correction This is a function that replaces a part of the program in the mask ROM with a program in the internal RAM for execution. Four points can be corrected. |
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Similar Description - UPD70F3201 |
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