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UPD70F3201 Datasheet(PDF) 22 Page - NEC |
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UPD70F3201 Datasheet(HTML) 22 Page - NEC |
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22 / 98 page  Preliminary Product Information U15436EJ1V0PM 22 µµµµPD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y 2. FUNCTION BLOCKS 2.1 Internal Units Each internal unit of the V850ES/SA2 and V850ES/SA3 is described below. (1) CPU The CPU uses five-stage pipeline control to enable 1-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32 bits), helps accelerate processing of complex instructions. (2) Bus control unit (BCU) The BCU starts the required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal instruction queue. (3) ROM This consists of a 256 KB mask ROM or flash memory mapped to the address space 0000000H to 003FFFFH. This area can be accessed by the CPU in 1-clock cycle when an instruction is fetched. (4) RAM This consists of a 16 KB RAM mapped to the address space 3FFB000H to 3FFEFFFH. This area can be accessed by the CPU in 1-clock cycle. (5) Interrupt controller (INTC) This controller services hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiple servicing control can be performed for interrupt sources. (6) Clock generator (CG) The clock generator includes two types of oscillators, one for the main clock (fXX) and one for the subclock (fXT), generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, fXX/16, and fXX/32), and supplies one of them as the operating clock for the CPU (fCPU). The subclock can only be selected as the operation clock of the real-time counter. (7) Timer/counter A two-channel 16-bit timer/event counter and a four-channel 8-bit timer/event counter are incorporated, which enables measurement of pulse intervals and frequency as well as programmable pulse output. Two channels of the 8-bit timer/event counter can be connected via a cascade connection to enable use as a 16-bit timer. |
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