TM124FBK32, TM124FBK32S 1048576 BY 32-BIT

TM248GBK32, TM248GBK32S 2097152 BY 32-BIT

DYNAMIC RAM MODULES

SMMS664A – DECEMBER 1995 – REVISED JUNE 1996

2

POST OFFICE BOX 1443

operation

TM124FBK32

The TM124FBK32 operates as eight TMS44409DJs connected as shown in the functional block diagram. Refer

to the TMS44409 data sheet for details of operation. The common I/O feature of the TM124FBK32 dictates the

use of early write cycles to prevent contention on D and Q.

TM248GBK32

The TM248GBK32 operates as sixteen TMS44409DJs connected as shown in the functional block diagram.

Refer to the TMS44409 data sheet for details of operation. The common I/O feature of the TM248GBK32

dictates the use of early write cycles to prevent contention on D and Q.

specifications

Refresh period is extended to 16 ms and, during this period, each of the 1 024 rows must be strobed with RAS

in order to retain data. A0–A9 address lines must be refreshed every 16 ms as required by the TMS44409

DRAM. CAS can remain high during the refresh sequence to conserve power.

single in-line memory module and components

PC substrate: 1,27

± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage

Bypass capacitors: Multilayer ceramic

Contact area for TM124FBK32 and TM248GBK32: Nickel plate and gold plate over copper

Contact area for TM124FBK32S and TM248GBK32S: Nickel plate and tin-lead over copper