TM124FBK32, TM124FBK32S 1048576 BY 32-BIT

TM248GBK32, TM248GBK32S 2097152 BY 32-BIT

DYNAMIC RAM MODULES

SMMS664A – DECEMBER 1995 – REVISED JUNE 1996

9

POST OFFICE BOX 1443

timing requirements over recommended range of supply voltage and operating free-air

temperature

’124FBK32-60

’248GBK32-60

’124FBK32-70

’248GBK32-70

’124FBK32-80

’248GBK32-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tRC

Cycle time, random read or write (see Note 7)

110

130

150

ns

tRWC

Cycle time, read-write

150

175

200

ns

tRASP

Pulse duration, page-mode, RAS low

60

100 000

70

100 000

80

100 000

ns

tRAS

Pulse duration, non-page-mode, RAS low

60

10 000

70

10 000

80

10 000

ns

tRP

Pulse duration, RAS high (precharge)

40

50

60

ns

tWP

Pulse duration, W low

10

10

10

ns

tRASS

Pulse duration, self-refresh entry from RAS low

100

100

100

µs

tRPS

Pulse duration, RAS precharge after self-refresh

110

130

150

ns

tASC

Setup time, column address before CAS low

0

0

0

ns

tASR

Setup time, row address before RAS low

0

0

0

ns

tDS

Setup time, data before CAS low

0

0

0

ns

tRCS

Setup time, W high before CAS low

0

0

0

ns

tCWL

Setup time, W low before CAS high

10

12

15

ns

tRWL

Setup time, W low before RAS high

10

12

15

ns

tWCS

Setup time, W low before CAS low

0

0

0

ns

tWRP

Setup time, W high before RAS low (see Note 8)

10

10

10

ns

tCAH

Hold time, column address after CAS low

10

15

15

ns

tDH

Hold time, data after CAS low

10

15

15

ns

tRAH

Hold time, row address after RAS low

10

10

10

ns

tRCH

Hold time, W high after CAS high (see Note 9)

0

0

0

ns

tRRH

Hold time, W high after RAS high (see Note 9)

0

0

0

ns

tWCH

Hold time, W low after CAS low

10

15

15

ns

tWRH

Hold time, W high after RAS low (see Note 8)

10

10

10

ns

tRHCP

Hold time, RAS high from CAS precharge

35

40

45

ns

tCHS

Hold time, CAS low after RAS high (self-refresh)

– 50

– 50

– 50

ns

tCHR

Delay time, RAS low to CAS high (see Note 8)

10

10

10

ns

tCRP

Delay time, CAS high to RAS low

5

5

5

ns

tCSR

Delay time, CAS low to RAS low (see Note 8)

5

5

5

ns

tRAD

Delay time, RAS low to column address (see Note 10)

15

30

15

35

15

40

ns

tRAL

Delay time, column address to RAS high

30

35

40

ns

tCAL

Delay time, column address to CAS high

20

25

30

ns

tRCD

Delay time, RAS low to CAS low (see Note 10)

20

45

20

52

20

60

ns

tRPC

Delay time, RAS high to CAS low (CBR only)

0

0

0

ns

tRSH

Delay time, CAS low to RAS high

10

12

15

ns

tREF

Refresh time interval

16

16

16

ms

tT

Transition time

2

30

2

30

2

30

ns

NOTES:

7. All cycled times assume tT = 5 ns.

8. CBR refresh only

9. Either tRRH or tRCH must be satisfied for a read cycle.

10. Maximum value specified only to assure access time.