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UPD780204 Datasheet(PDF) 24 Page - NEC |
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UPD780204 Datasheet(HTML) 24 Page - NEC |
24 / 418 page 24 User’s Manual U11302EJ4V0UM CHAPTER 1 OUTLINE 1.1 Features Internal high-capacity ROM and RAM Item Program Memory Data Memory Part ROM PROM Internal High- Buffer RAM VFD Display Internal Number Speed RAM RAM Expansion RAM µPD780204 32 KB — 1024 bytes 64 bytes 80 bytes None µPD780204A µPD780205 40 KB — µPD780205A µPD780206 48 KB — 1024 bytes µPD780208 60 KB — µPD78P0208 — 60 KBNote 1 1024 bytesNote 2 Notes 1. 32, 40, 48, or 60 KB can be selected by setting the internal memory size switching register (IMS). 2. 0 or 1024 bytes can be selected by setting the internal expansion RAM size switching register (IXS). Minimum instruction execution time can be changed from high speed (0.4 µs: @ 5.0 MHz operation with main system clock) to ultra-low speed (122 µs: @ 32.768 kHz operation with subsystem clock) 74 I/O ports VFD controller/driver: 53 display outputs in total • Segments: 9 to 40 • Digits: 2 to 16 8-bit resolution A/D converter: 8 channels • Power supply voltage (AVDD = 4.0 to 5.5 V) Serial interface: 2 channels • 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel • 3-wire serial I/O mode (automatic transmit/receive function): 1 channel Timer: 5 channels • 16-bit timer/event counter: 1 channel • 8-bit timer/event counter: 2 channels • Watch timer: 1 channel • Watchdog timer: 1 channel 15 vectored interrupt sources One test input Two types of on-chip clock oscillators (for main and subsystem clocks) Power supply voltage: VDD = 2.7 to 5.5 V |
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