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KSZ9021RL Datasheet(PDF) 10 Page - Microchip Technology |
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KSZ9021RL Datasheet(HTML) 10 Page - Microchip Technology |
10 / 67 page KSZ9021RL/RN DS00003050A-page 10 2009-2019 Microchip Technology Inc. 32 GTX_CLK I RGMII Mode: RGMII TXC (Transmit Reference Clock) Input 33 TX_EN I RGMII Mode: RGMII TX_CTL (Transmit Control) Input 34 VSS Gnd Digital ground 35 DVDDL P 1.2V digital V DD 36 RXD3 / MODE3 I/O RGMII Mode: RGMII RD3 (Receive Data 3) Output / Config Mode: The pull-up/pull-down value is latched as MODE3 during power-up/ reset. See “Strapping Options” section for details. 37 DVDDH P 3.3V/2.5V digital V DD 38 RXD2 / MODE2 I/O RGMII Mode: RGMII RD2 (Receive Data 2) Output / Config Mode: The pull-up/pull-down value is latched as MODE2 during power- up/reset. See “Strapping Options” section for details. 39 VSS Gnd Digital ground 40 DVDDL P 1.2V digital V DD 41 RXD1 / MODE1 I/O RGMII Mode: RGMII RD1 (Receive Data 1) Output / Config Mode: The pull-up/pull-down value is latched as MODE1 during power-up/ reset. See “Strapping Options” section for details. 42 RXD0 / MODE0 I/O RGMII Mode: RGMII RD0 (Receive Data 0) Output / Config Mode: The pull-up/pull-down value is latched as MODE0 during power-up/ reset. See “Strapping Options” section for details. 43 RX_DV / CLK125_EN I/O RGMII Mode: RGMII RX_CTL (Receive Control) Output / Config Mode: Latched as CLK125_NDO Output Enable during power-up/reset. See “Strapping Options” section for details. 44 DVDDH P 3.3V/2.5V digital V DD 45 RX_ER O RGMII Mode: This pin is not used and should be left as a no connect. 46 RX_CLK / PHYAD2 I/O RGMII Mode: RGMII RXC (Receive Reference Clock) Output / Config Mode: The pull-up/pull-down value is latched as PHYAD[2] during power- up/reset. See “Strapping Options” section for details. 47 CRS O RGMII Mode: This pin is not used and should be left as a no connect. Pin Number Pin Name Type (Note 1) Pin Function |
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