Philips Semiconductors

Product data

SCC2681T

Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

9

5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle

and the signal negated first terminates the cycle.

6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must

RDN input even if the CEN is used as the strobing signal for bus operations.

7. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.

8. Minimum frequencies are not tested but are guaranteed by design.

SD00028

RESET

tRES

Figure 3. Reset Timing

A0–A3

CEN

(READ)

tAVEL

RDN

D0–D7

(READ)

FLOAT

FLOAT

VALID

INVALID

CEN

(WRITE)

VALID

D0–D7

(WRITE)

tELAX

tEHEL

tRLRH

tRHDF

tRHDI

tRLDV

tRLDA

tEHEL

tWLWH

WRN

tDVWH

tWHDI

SD00100

Figure 4. Bus Timing