Philips Semiconductors

Product data

SCC2681T

Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

8

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Typ

Max

UNIT

Reset timing (see Figure 3)

Reset pulse width

1.0

–

–

µs

Bus timing (see Figure 4) (Note 5)

A0–A3 set-up to RDN and CEN, or WRN and CEN LOW

0

–

–

ns

RDN and CEN, or WRN and CEN LOW to A0–A3 invalid

100

–

–

ns

RDN and CEN LOW to RDN or CEN HIGH

120

–

–

ns

110

–

–

ns

CEN and RDN LOW to data outputs active

15

–

–

ns

CEN and RDN LOW to data valid

–

–

100

ns

CEN or RDN HIGH to data invalid

10

–

–

ns

CEN or RDN HIGH to data outputs floating

–

–

65

ns

WRN and CEN LOW to WRN or CEN HIGH

75

–

–

ns

Data input valid to WRN or CEN HIGH

35

–

–

ns

WRN or CEN HIGH to data invalid

15

–

–

ns

Port timing (see Figure 5)

Port input set-up time before RDN LOW

0

–

–

ns

Port input hold time after RDN HIGH

0

–

–

ns

Port output valid after WRN HIGH

–

–

200

ns

Interrupt timing (see Figure 6)

INTRN (or OP3–OP7 when used as interrupts) negated from:

Read RHR (RxRDY/FFULL interrupt)

–

–

200

ns

Write THR (TxRDY interrupt)

–

–

200

ns

Reset command (delta break interrupt)

–

–

200

ns

Stop C/T command (counter interrupt)

–

–

200

ns

Read IPCR (input port change interrupt)

–

–

200

ns

Write IMR (clear of interrupt mask bit)

–

–

200

ns

Clock timing (see Figure 7)

X1/CLK HIGH or LOW time

90

ns

X1/CLK frequency

2

4

MHz

CTCLK (IP2) HIGH or LOW time

55

ns

0

8

MHz

RxC HIGH or LOW time

55

ns

f

RxC frequency

(16

0

3.6864

8

MHz

(1

0

1

MHz

TxC HIGH or LOW time

110

ns

TxC frequency

(16

0

4

MHz

(1

0

1

MHz

Transmit timing (see Figure 8)

TxD output delay from TxC external clock input on IP pin

–

–

300

ns

Output delay from TxC LOW at OP pin to TxD data output

0

–

100

ns

Receive timing (see Figure )

RxD data set-up time before RxC HIGH at external clock input on IP pin

200

–

–

ns

RxD data hold time after RxC HIGH at external clock input on IP pin

25

–

–

ns

NOTES:

supply range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a

transition time of 20 ns maximum. For X1/CLK this swing is between 0.4 V and 4.0 V. All time measurements are referenced at input

voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V as appropriate.

3. Typical values are at +25

°C, typical supply voltages, and typical processing parameters.