Philips Semiconductors

Product data

SCC2681T

Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

4

PIN CONFIGURATION

6

40

41

42

43

44

1

2

IP2

IP6

IP5

IP4

VCC

A0

n.c.

3

4

5

IP3

A1

A2

IP1

18

28

27

26

25

24

23

22

21

20

19

D0

D2

D4

D6

INTRN

GND

n.c.

D7

D5

D1

D3

SCC2681TC1A44

SD00737

Figure 2. Pin configuration

PIN DESCRIPTION

MNEMONIC

PIN

TYPE

NAME AND FUNCTION

D0–D7

21, 25, 20,

26, 19, 27,

18, 28

I/O

Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the

DUART and the CPU. D0 is the least significant bit.

CEN

39

I

Chip Enable: Active LOW input signal. When LOW, data transfers between the CPU and the DUART

are enabled on D0–D7 as controlled by the WRN, RDN, and A0–A3 inputs. When CEN is HIGH, the

DUART places the D0–D7 lines in the three-state condition.

WRN

9

I

Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is loaded into the

addressed register. The transfer occurs on the rising edge of the signal.

RDN

10

I

Read Strobe: When low and CEN is also LOW, causes the contents of the addressed register to be

presented on the data bus. The read cycle begins on the falling edge of RDN.

A0–A3

2, 4, 6, 7

I

Address Inputs: Select the DUART internal registers and ports for read/write operations.

RESET

38

I

Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the

HIGH state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and

TxDB outputs in the mark (HIGH) state. Clears Test modes, sets MR pointer to MR1.

INTRN

24

O

Interrupt Request: Active-LOW, open-drain output which signals the CPU that one or more of the eight

maskable interrupting conditions are true.

X1/CLK

36

I

Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency

(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock

Timing.

X2

37

I

Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not

connected.

It must not be grounded.

RxDA

35

I

Channel A Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is HIGH, ‘space’

is LOW.

RxDB

11

I

Channel B Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is HIGH, ‘space’

is LOW.