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AT90S8535 Datasheet(PDF) 62 Page - ATMEL Corporation |
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AT90S8535 Datasheet(HTML) 62 Page - ATMEL Corporation |
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62 / 127 page  62 AT90S/LS8535 1041H–11/01 UART Control UART I/O Data Register – UDR The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read. UART Status Register – USR The USR register is a read-only register providing information on the UART status. • Bit 7 – RXC: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift reg- ister to UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. • Bit 6 – TXC: UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting appli- cation must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical “1” to the bit. • Bit 5 – UDRE: UART Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit Shift register. Setting of this bit indicates that the transmitter is ready to receive a new charac- ter for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be exe- cuted as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt rou- tine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready. • Bit 4 – FE: Framing Error This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom- ing character is zero. Bit 765 432 10 $0C ($2C) MSB LSB UDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 432 10 $0B ($2B) RXC TXC UDRE FE OR –– – USR Read/Write R R/W R R R R R R Initial Value 0 0 1 0 0 0 0 0 |
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Similar Description - AT90S8535 |
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