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AT90S8535 Datasheet(PDF) 48 Page - ATMEL Corporation |
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AT90S8535 Datasheet(HTML) 48 Page - ATMEL Corporation |
48 / 127 page ![]() 48 AT90S/LS8535 1041H–11/01 least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. • During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least 1 before the processor can read the timer value causing the setting of the interrupt flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock. |
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