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AT90S8535 Datasheet(PDF) 46 Page - ATMEL Corporation |
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AT90S8535 Datasheet(HTML) 46 Page - ATMEL Corporation |
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46 / 127 page  46 AT90S/LS8535 1041H–11/01 In PWM mode, the Timer Overflow Flag (TOV2) is set when the counter advances from $00. Timer Overflow Interrupt2 operates exactly as in normal Timer/Counter mode, i.e., it is executed when TOV2 is set, provided that Timer Overflow Interrupt and global inter- rupts are enabled. This also applies to the Timer Output Compare flag and interrupt. The frequency of the PWM will be Timer Clock Frequency divided by 510. Asynchronous Status Register – ASSR • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the AT90S8535 and always read as zero. • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is set (one), Timer/Counter2 is clocked from the TOSC1 pin. Pins PC6 and PC7 become connected to a crystal oscillator and cannot be used as general I/O pins. When cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When the value of this bit is changed, the contents of TCNT2, OCR2 and TCCR2 might get corrupted. • Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that TCNT2 is ready to be updated with a new value. • Bit 1 – OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that OCR2 is ready to be updated with a new value. • Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical “0” in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 registers while its Update Busy flag is set (one), the updated value might get corrupted and cause an unintentional inter- rupt to occur. The mechanisms for reading TCNT2, OCR2 and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read. 10 $FF H 11 $00 H 11 $FF L Table 20. PWM Outputs OCR2 = $00 or $FF COM21 COM20 OCR2 Output PWM2 Bit 7 65 43 2 1 0 $22 ($22) –– –– AS2 TCN2UB OCR2UB TCR2UB ASSR Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0 |
Similar Part No. - AT90S8535 |
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Similar Description - AT90S8535 |
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