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AT90S8535 Datasheet(PDF) 23 Page - ATMEL Corporation |
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AT90S8535 Datasheet(HTML) 23 Page - ATMEL Corporation |
23 / 127 page 23 AT90S/LS8535 1041H–11/01 Figure 24. MCU Start-up, RESET Tied to V CC. Figure 25. MCU Start-up, RESET Controlled Externally External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (V RST) on its positive edge, the delay timer starts the MCU after the Time-out period t TOUT has expired. Figure 26. External Reset during Operation VCC RESET TIME-OUT INTERNAL RESET t TOUT V POT V RST VCC RESET TIME-OUT INTERNAL RESET t TOUT V POT V RST |
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