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AT90S8535 Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT90S8535 Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 127 page  8 AT90S/LS8535 1041H–11/01 assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The program memory is executed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The pro- gram memory is in-system downloadable Flash memory. With the relative jump and call instructions, the whole 4K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM and consequently, the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 10-bit stack pointer (SP) is read/write-accessible in the I/O space. The 512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. Figure 5. Memory Maps A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a sepa- rate interrupt vector in the interrupt vector table at the beginning of the program 32 Gen. Purpose Working Registers 64 I/O Registers Internal SRAM (512 x 8) $0000 $001F $005F $0060 $025F $0020 $000 $FFF Data Memory Program Memory Program Flash (4K x 16) EEPROM (512 x 8) $000 $1FF Data Memory |
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