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AT90S8535 Datasheet(PDF) 73 Page - ATMEL Corporation |
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AT90S8535 Datasheet(HTML) 73 Page - ATMEL Corporation |
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73 / 127 page  73 AT90S/LS8535 1041H–11/01 ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a extended conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a “0” to this bit has no effect. • Bit 5 – ADFR: ADC Free Running Select When this bit is set (one), the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete interrupt is executed if the ADIE bit and the I- bit in SREG are set (one). ADIF is cleared by hardware when executing the correspond- ing interrupt handling vector. Alternatively, ADIF is cleared by writing a logical “1” to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be dis- abled. This also applies if the SBI and CBI instructions are used. • Bit 3 – ADIE: ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com- plete interrupt is activated. • Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. ADC Data Register – ADCL AND ADCH When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse- quently, it is essential that both registers are read and that ADCL is read before ADCH. Table 28. ADC Prescaler Selections ADPS2 ADPS1 ADPS0 Division Factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Bit 15 1413 12 1110 9 8 $05 ($25) ––– ––– ADC9 ADC8 ADCH $04 ($24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 765 432 10 Read/Write RR RRR RRR RR RRR RRR Initial Value 0 0 0 0 0 0 0 0 000 000 00 |
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