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AT90S8535 Datasheet(PDF) 72 Page - ATMEL Corporation |
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AT90S8535 Datasheet(HTML) 72 Page - ATMEL Corporation |
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72 / 127 page  72 AT90S/LS8535 1041H–11/01 2. Enter Idle Mode. The ADC will start a conversion once the CPU has been halted. 3. If no other interrupts occur before the ADC conversion completes, the ADC inter- rupt will wake up the MCU and execute the ADC Conversion Complete Interrupt routine. ADC Multiplexer Select Register – ADMUX • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S8535 and always read as zero. • Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2-0 The value of these three bits selects which analog input ADC7..0 is connected to the ADC. See Table 27 for details. If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSR is set). ADC Control and Status Register – ADCSR • Bit 7 – ADEN: ADC Enable Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress will terminate this conversion. • Bit 6 – ADSC: ADC Start Conversion In Single Conversion Mode, a logical “1” must be written to this bit to start each conver- sion. In Free Running Mode, a logical “1” must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled or if ADSC is written at the same time as the ADC is enabled, an extended conversion will precede the initiated conversion. This extended conversion performs initialization of the ADC. Bit 765 432 10 $07 ($27) ––– –– MUX2 MUX1 MUX0 ADMUX Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 27. Input Channel Selections MUX2.0 Single-ended Input 000 ADC0 001 ADC1 010 ADC2 011 ADC3 100 ADC4 101 ADC5 110 ADC6 111 ADC7 Bit 765 432 10 $06 ($26) ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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