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AT90S8535 Datasheet(PDF) 70 Page - ATMEL Corporation |
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AT90S8535 Datasheet(HTML) 70 Page - ATMEL Corporation |
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70 / 127 page  70 AT90S/LS8535 1041H–11/01 higher sampling rate. See “ADC Characteristics” on page 75 for more details. The ADC module contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADPS2..0 bits in ADCSR are used to generate a proper ADC clock input frequency from any CPU frequency above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler keeps running for as long as the ADEN bit is set and is continuously reset when ADEN is low. When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs more clock cycles for initialization and to minimize offset errors. Extended conversions take 25 ADC clock cycles and occur as the first conversion after the ADC is switched on (ADEN in ADCSR is set). The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an extended conversion. When a conversion is complete, the result is written to the ADC data registers and ADIF is set. In Single Conversion Mode, ADSC is cleared simultaneously. The software may then set ADSC again and a new conversion will be initiated on the first rising ADC clock edge. In Free Running Mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. Using Free Running Mode and an ADC clock frequency of 200 kHz gives the lowest conversion time with a maximum res- olution, 65 µs, equivalent to 15 kSPS. For a summary of conversion times, see Table 26. Figure 47. ADC Timing Diagram, Extended Conversion (Single Conversion Mode) Sign and MSB of result LSB of result ADC clock ADSC Sample & hold ADIF ADCH ADCL Cycle number ADEN 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 Extended Conversion Next Conversion 3 MUX and REFS update MUX and REFS update Conversion complete |
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