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X24C45 Datasheet(PDF) 8 Page - Intersil Corporation |
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X24C45 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 12 page ![]() 8 FN8104.0 June 1, 2005 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read and Write Cycle Limits POWER-UP TIMING Notes: (3) SK rise and fall times must be less than 50ns. (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 5V 919 Ω 497 Ω Output 100pF Input pulse levels 0V to 3V Input rise and fall times 10ns Input and output timing levels 1.5V Symbol Parameter Min. Max. Unit FSK(3) SK frequency 1 MHz tSKH SK positive pulse width 400 ns tSKL SK negative pulse width 400 ns tDS Data setup time 400 ns tDH Data hold time 80 ns tPD1 SK to data bit 0 valid 375 ns tPD SK to data valid 375 ns tZ Chip enable to output high Z 1 µs tCES Chip enable setup 800 ns tCEH Chip enable hold 350 ns tCDS Chip deselect 800 ns Symbol Parameter Max. Unit tPUR(4) Power-up to read operation 200 µs tPUW(4) Power-up to write or store operation 5 ms X24C45 |
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