D-Type

Flip-Flop

Counter

2

0

2

1

2

2

2

3

2

4

Input

Clear

Q

CLR

Q

D

CLR

9

SN74HCS14

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SCLS799 – JANUARY 2020

Product Folder Links: SN74HCS14

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74HCS14 can be used to add an additional stage to a counter with an external flip-flop. Because

counters use a negative edge trigger, the flip-flop's clock input must be inverted to provide this function. Having

Schmitt-trigger inputs is important in this application to eliminate any noise issues that could impact the counting

function which could lead to incorrect frequency division. This function only requires one of the six available

inverters in the SN74HCS14 device, so the remaining channels can be used for other applications needing an

can be left floating.

9.2 Typical Application

Figure 9. Typical application block diagram

9.2.1 Design Requirements

•

All logic devices shown are operating from the same 5-V supply

•

Each device must have an individual bypass capacitor as described in

•

There are no limitations on input edge rates to the SN74HCS14 due to Schmitt-trigger inputs

9.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The

supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.

The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the

only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to

The SN74HCS14 can drive a load with a total capacitance less than or equal to 50 pF connected to a high-

impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be

applied, however it is not recommended to exceed 70 pF.

Total power consumption can be calculated using the information provided in CMOS Power Consumption and

Cpd Calculation.

Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear

and Logic (SLL) Packages and Devices.