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LMV321A Datasheet(PDF) 23 Page - Texas Instruments |
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LMV321A Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 48 page  OUT1 IN1 ± IN1 + V ± OUT2 IN2 ± IN2 + V+ VS± GND Ground (GND) plane on another layer Keep input traces short and run the input traces as far away from the supply lines as possible . Place components close to device and to each other to reduce parasitic errors . Use low-ESR, ceramic bypass capacitor . Place as close to the device as possible . VIN 1 GND RF RG VIN 2 GND RF RG VS+ GND OUT 1 OUT 2 Use low-ESR, ceramic bypass capacitor . Place as close to the device as possible . + VIN 2 VOUT 2 R G R F + VIN 1 VOUT 1 R G R F 23 LMV321A, LMV324A, LMV358A www.ti.com SBOS923F – DECEMBER 2017 – REVISED JANUARY 2020 Product Folder Links: LMV321A LMV324A LMV358A Submit Documentation Feedback Copyright © 2017–2020, Texas Instruments Incorporated 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good printed circuit board (PCB) layout practices, including: • Noise can propagate into analog circuitry through the power connections of the board and propagate to the power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a low-impedance path to ground. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single- supply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current. • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as opposed to running the traces in parallel with the noisy trace. • Place the external components as close to the device as possible, as shown in Figure 39. Keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce leakage currents from nearby traces that are at different potentials. • Cleaning the PCB following board assembly is recommended for best performance. • Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. 10.2 Layout Example Figure 38. Schematic Representation for Figure 39 Figure 39. Layout Example |
Similar Part No. - LMV321A_V02 |
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Similar Description - LMV321A_V02 |
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