MC14584BCP datasheet(1/8 Pages) ONSEMI

Part #	MC14584BCP

Description	Hex Schmitt Trigger

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March, 2000 – Rev. 3

1

Publication Order Number:

MC14584B/D

MC14584B

Hex Schmitt Trigger

The MC14584B Hex Schmitt Trigger is constructed with MOS

P–channel and N–channel enhancement mode devices in a single

monolithic structure. These devices find primary use where low power

dissipation and/or high noise immunity is desired. The MC14584B

may be used in place of the MC14069UB hex inverter for enhanced

noise immunity to “square up” slowly changing waveforms.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load over the Rated Temperature Range

• Double Diode Protection on All Inputs

• Can Be Used to Replace MC14069UB

• For Greater Hysteresis, Use MC14106B which is Pin–for–Pin

Replacement for CD40106B and MM74Cl4

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage Range

– 0.5 to +18.0

V

Vin, Vout

Input or Output Voltage Range

(DC or Transient)

– 0.5 to VDD + 0.5

V

Iin, Iout

Input or Output Current

(DC or Transient) per Pin

±10

mA

PD

Power Dissipation,

per Package (Note 3.)

500

mW

TA

Ambient Temperature Range

– 55 to +125

°C

Tstg

Storage Temperature Range

– 65 to +150

°C

TL

Lead Temperature

(8–Second Soldering)

260

°C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high–impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either VSS or VDD). Unused outputs must be left open.

http://onsemi.com

A

= Assembly Location

WL or L

= Wafer Lot

YY or Y

= Year

WW or W = Work Week

MARKING

DIAGRAMS

1

14

PDIP–14

P SUFFIX

CASE 646

MC14584BCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

TSSOP–14

DT SUFFIX

CASE 948G

1

14

14584B

AWLYWW

14

584B

ALYW

1

14

SOEIAJ–14

F SUFFIX

CASE 965

1

14

MC14584B

AWLYWW

Device

Package

Shipping

ORDERING INFORMATION

MC14584BCP

PDIP–14

2000/Box

MC14584BD

SOIC–14

55/Rail

MC14584BDR2

SOIC–14

2500/Tape & Reel

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local

ON Semiconductor representative.

MC14584BDTEL

TSSOP–14 2000/Tape & Reel

MC14584BDT

TSSOP–14

96/Rail

MC14584BF

SOEIAJ–14

See Note 1.

MC14584BFEL

SOEIAJ–14

See Note 1.

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