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LTC2439-1 Datasheet(PDF) 22 Page - Linear Technology |
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LTC2439-1 Datasheet(HTML) 22 Page - Linear Technology |
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22 / 28 page  LTC2439-1 22 24391f The effect of this input dynamic current can be analyzed using the test circuit of Figure 13. The CPAR capacitor includes the LTC2439-1 pin capacitance (5pF typical) plus the capacitance of the test fixture used to obtain the results shown in Figures 14 and 15. A careful implementation can bring the total input capacitance (CIN + CPAR) closer to 5pF thus achieving better performance than the one predicted by Figures 14 and 15. For simplicity, two distinct situa- tions can be considered. For relatively small values of input capacitance (CIN < 0.01 µF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CIN will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them. Nevertheless, when small values of CIN are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the LTC2439-1 can maintain its accuracy while operating with relative large values of source resistance as shown in Figures 14 and 15. These measured results may be slightly different from the first order approximation suggested earlier because they include the effect of the actual second order input network together with the nonlinear settling process of the input amplifiers. For small CIN values, the settling on IN+ and IN– occurs almost independently and there is little benefit in trying to match the source imped- ance for the two pins. Larger values of input capacitors (CIN > 0.01µF) may be required in certain configurations for antialiasing or gen- eral input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. When FO = LOW (internal oscillator and 50Hz/60Hz notch), the typical differential input resistance is 2M Ω which will generate a gain error of approximately 1LSB at full scale for each 60 Ω of source resistance driving IN+ or IN–. When FO is driven by an external oscillator with a fre- quency fEOSC (external conversion clock operation), the typical differential input resistance is 0.28 • 1012/fEOSCΩ RSOURCE (Ω) 1 10 100 1k 10k 100k 24361 F14 3 0 1 2 VCC = 5V REF+ = 5V REF – = GND IN+ = 5V IN– = 2.5V FO = GND TA = 25°C CIN = 0.01µF CIN = 0.001µF CIN = 100pF CIN = 0pF CIN 24361 F13 VINCM + 0.5VIN RSOURCE IN+ LTC2439-1 CPAR ≅20pF CIN VINCM – 0.5VIN RSOURCE IN – CPAR ≅20pF Figure 13. An RC Network at IN+ and IN– RSOURCE (Ω) 1 10 100 1k 10k 100k 24361 F15 0 –3 –2 –1 VCC = 5V REF+ = 5V REF – = GND IN+ = GND IN– = 2.5V FO = GND TA = 25°C CIN = 0.01µF CIN = 0.001µF CIN = 100pF CIN = 0pF Figure 14. +FS Error vs RSOURCE at IN+ or IN– (Small CIN) Figure 15. –FS Error vs RSOURCE at IN + or IN– (Small CIN) APPLICATIO S I FOR ATIO |
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