 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LTC2439-1 Datasheet(PDF) 20 Page - Linear Technology |
|
|
|||||||||||||||||||||||||||||
LTC2439-1 Datasheet(HTML) 20 Page - Linear Technology |
|
|
20 / 28 page  LTC2439-1 20 24391f Digital Signal Levels The LTC2439-1’s digital interface is easy to use. Its digital inputs (SDI, FO, CS and SCK in External SCK mode of operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100 µs. However, some considerations are required to take advantage of the accuracy and low supply current of this converter. The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state. While a digital input signal is in the range 0.5V to (VCC – 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (SDI, FO, CS and SCK in External SCK mode of operation) is within this range, the power supply current may increase even if the signal in question is at a valid logic level. For micropower operation, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)]. During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the pins may severely disturb the analog to digital conversion process. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2439- 1. For reference, on a regular FR-4 board, signal propaga- tion velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance. Parallel termination near the LTC2439-1 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 Ω and 56Ω placed near the driver or near the LTC2439-1 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. An alternate solution is to reduce the edge rate of the control signals. It should be noted that using very slow edges will increase the converter power supply current during the transition time. The differential input and refer- ence architecture reduce substantially the converter’s sensitivity to ground currents. Particular attention must be given to the connection of the FO signal when the LTC2439-1 is used with an external conversion clock. This clock is active during the conver- sion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the converter reference terminals may result into DC gain and INL errors. A normal mode signal of this frequency at the converter input terminals may result into a DC offset error. Such perturbations may occur due to asymmetric capaci- tive coupling between the FO signal trace and the converter input and/or reference connection traces. An immediate solution is to maintain maximum possible separation between the FO signal trace and the input/reference sig- nals. When the FO signal is parallel terminated near the converter, substantial AC current is flowing in the loop formed by the FO connection trace, the termination and the ground return path. Thus, perturbation signals may be inductively coupled into the converter input and/or refer- ence. In this situation, the user must reduce to a minimum the loop area for the FO signal as well as the loop area for the differential input and reference connections. Driving the Input and Reference The input and reference pins of the LTC2439-1 converter are directly connected to a network of sampling capaci- tors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transfer- ring small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 12. For a simple approximation, the source impedance RS driving an analog input pin (IN+, IN–, REF+ or REF–) can be considered to form, together with RSW and CEQ (see APPLICATIO S I FOR ATIO |
Similar Part No. - LTC2439-1 |
|
Similar Description - LTC2439-1 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
