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LTC2439-1 Datasheet(PDF) 19 Page - Linear Technology |
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LTC2439-1 Datasheet(HTML) 19 Page - Linear Technology |
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19 / 28 page  LTC2439-1 19 24391f Internal Serial Clock, 3-Wire I/O, Continuous Conversion This timing mode uses a 3-wire interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 11. CS may be perma- nently tied to ground, simplifying the user interface or isolation barrier. The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after VCC exceeds 2V. An internal weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data input/ output cycle begins on the first rising edge of SCK and ends after the 19th rising edge. The input data is then shifted in via the SDI pin on the rising edge of SCK (including the first rising edge) and the output data is shifted out of the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 19th rising edge of SCK. After the 19th rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. PRESERVING THE CONVERTER ACCURACY The LTC2439-1 is designed to reduce as much as possible the conversion result sensitivity to device decoupling, PCB layout, antialiasing circuits, line fre- quency perturbations and so on. Nevertheless, in order to preserve the accuracy capability of this part, some simple precautions are desirable. APPLICATIO S I FOR ATIO Figure 11. Internal Serial Clock, CS = 0 Continuous Operation (1) (0) EN SGL A2 A1 A0 ODD/ SIGN SDI DON’T CARE DON’T CARE SDO SCK (INTERNAL) CS MSB SIG BIT 6 BIT 0 LSB BIT 14 BIT 13 BIT 12 BIT 11 BIT 15 BIT 16 BIT 17 EOC BIT 18 DATA OUTPUT CONVERSION CONVERSION 24391 F10 VCC FO REF+ REF– CH0 CH7 CH8 CH15 COM SCK SDI SDO CS GND 920 11 12 21 28 1 8 10 18 17 15 16 19 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUTS 1 µF 2.7V TO 5.5V LTC2439-1 3-WIRE SPI INTERFACE • • • • • • • • • • • • = EXTERNAL CLOCK SOURCE = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION “O” |
Similar Part No. - LTC2439-1 |
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Similar Description - LTC2439-1 |
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