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LTC2439-1 Datasheet(PDF) 18 Page - Linear Technology |
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LTC2439-1 Datasheet(HTML) 18 Page - Linear Technology |
18 / 28 page ![]() LTC2439-1 18 24391f Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 19th rising edge of SCK, see Figure 10. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. If the device has not finished loading the last input bit (A0 of SDI) by the time CS is pulled HIGH, the address information is discarded and the previous ad- dress is still kept. This is useful for aborting an invalid conversion cycle, or synchronizing the start of a conver- sion. If CS is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW. Whenever SCK is LOW, the LTC2439-1’s internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2439-1’s internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pull-up resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode. A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conver- sion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin. APPLICATIO S I FOR ATIO Figure 10. Internal Serial Clock, Reduced Data Output Length (1) (0) EN SGL A2 A1 A0 ODD/ SIGN SDI DON’T CARE DON’T CARE SDO SCK (INTERNAL) CS >tEOCtest MSB SIG BIT 4 TEST EOC (OPTIONAL) TEST EOC BIT 14 BIT 13 BIT 12 BIT 11 BIT 15 BIT 16 BIT 17 EOC BIT 18 EOC BIT 0 SLEEP SLEEP DATA OUTPUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DATA OUTPUT CONVERSION CONVERSION SLEEP 24391 F09 <tEOCtest VCC 10k TEST EOC VCC FO REF+ REF– CH0 CH7 CH8 CH15 COM SCK SDI SDO CS GND 920 11 12 21 28 1 8 10 18 17 15 16 19 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUTS 1 µF 2.7V TO 5.5V LTC2439-1 4-WIRE SPI INTERFACE • • • • • • • • • • • • = EXTERNAL CLOCK SOURCE = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION “O” |
Similar Part No. - LTC2439-1 |
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Similar Description - LTC2439-1 |
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