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LTC2439-1 Datasheet(PDF) 17 Page - Linear Technology |
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LTC2439-1 Datasheet(HTML) 17 Page - Linear Technology |
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17 / 28 page  LTC2439-1 17 24391f APPLICATIO S I FOR ATIO Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 9. In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is auto- matically selected if SCK is not externally driven. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the conversion is complete. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the low power mode during the EOC test. In order to allow the device to return to the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of tEOCtest is 23µs if the device is using its internal oscillator (FO = logic LOW or HIGH). If FO is driven by an external oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device returns to the sleep state and the conversion result is held in the internal static shift register. If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data I/O cycle concludes after the 19th rising edge. The input data is then shifted in via the SDI pin on the rising edge of SCK (including the first rising edge) and the output data is shifted out of the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 19th rising edge of SCK. After the 19th rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH and a new conversion starts. Figure 9. Internal Serial Clock, Single Cycle Operation (1) (0) EN SGL A2 A1 A0 ODD/ SIGN SDI DON’T CARE DON’T CARE SDO SCK (INTERNAL) CS MSB SIG BIT 0 LSB BIT 6 TEST EOC BIT 14 BIT 13 BIT 12 BIT 11 BIT 15 BIT 16 BIT 17 EOC BIT 18 SLEEP SLEEP DATA OUTPUT CONVERSION CONVERSION 24391 F08 <tEOCtest Hi-Z Hi-Z Hi-Z Hi-Z TEST EOC VCC FO REF+ REF– CH0 CH7 CH8 CH15 COM SCK SDI SDO CS GND 920 11 12 21 28 1 8 10 18 17 15 16 19 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUTS 1 µF 2.7V TO 5.5V LTC2439-1 4-WIRE SPI INTERFACE • • • • • • • • • • • • VCC 10k = EXTERNAL CLOCK SOURCE = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION “O” |
Similar Part No. - LTC2439-1 |
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Similar Description - LTC2439-1 |
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