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LTC2439-1 Datasheet(PDF) 15 Page - Linear Technology |
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LTC2439-1 Datasheet(HTML) 15 Page - Linear Technology |
15 / 28 page ![]() LTC2439-1 15 24391f APPLICATIO S I FOR ATIO Figure 6. External Serial Clock, Single Cycle Operation EOC BIT 18 SDO SCK (EXTERNAL) CS (1) (0) EN SGL A2 A1 A0 ODD/ SIGN SDI DON’T CARE TEST EOC LBS MSB SIG BIT 0 BIT 6 BIT 14 BIT 13 BIT 12 BIT 11 BIT 15 BIT 16 BIT 17 SLEEP SLEEP DATA OUTPUT CONVERSION 24391 F05 CONVERSION Hi-Z Hi-Z Hi-Z TEST EOC VCC FO REF+ REF– CH0 CH7 CH8 CH15 COM SCK SDI SDO CS GND 920 11 12 21 28 1 8 10 18 17 15 16 19 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUTS 1 µF 2.7V TO 5.5V LTC2439-1 4-WIRE SPI INTERFACE • • • • • • • • • • • • DON’T CARE TEST EOC (OPTIONAL) = EXTERNAL CLOCK SOURCE = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION (0) is seen while CS is LOW. The input data is then shifted in via the SDI pin on the rising edge of SCK (including the first rising edge) and the output data is shifted out of the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 19th rising edge of SCK. On the 19th falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first rising edge and the19th falling edge of SCK, see Figure 7. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. If the device has not finished loading the last input bit A0 of SDI by the time CS is pulled HIGH, the address information is discarded and the previ- ous address is kept. This is useful for aborting an invalid conversion cycle or synchronizing the start of a conversion. External Serial Clock, 3-Wire I/O This timing mode utilizes a 3-wire serial I/O interface. The conversion result is shifted out of the device by an exter- nally generated serial clock (SCK) signal, see Figure 8. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded typically 1ms after VCC exceeds approximately 2V. The level applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode. Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion ends. On the falling edge of EOC, the conversion result is loaded into an internal static |
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