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LTC2439-1 Datasheet(PDF) 14 Page - Linear Technology |
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LTC2439-1 Datasheet(HTML) 14 Page - Linear Technology |
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14 / 28 page  LTC2439-1 14 24391f Finally, CS can be used to control the free-running mode of operation, see Serial Interface Timing Modes section. Grounding CS will force the ADC to continuously convert at the maximum output rate selected by FO. SERIAL INTERFACE TIMING MODES The LTC2439-1’s 4-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 3- or 4-wire I/O, single cycle conversion. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW) or an external oscillator connected to the FO pin. Refer to Table 6 for a summary. External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 6. The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the conversion is complete. If CS is HIGH, the device automatically enters the low power sleep state once the conversion is complete. When the device is in the sleep state, its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK Table 6. LTC2439-1 Interface Timing Modes Conversion Data Connection SCK Cycle Output and Configuration Source Control Control Waveforms External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 6, 7 External SCK, 3-Wire I/O External SCK SCK Figure 8 Internal SCK, Single Cycle Conversion Internal CS ↓ CS ↓ Figures 9, 10 Internal SCK, 3-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 11 When CS (Pin 16) is HIGH or the converter is in the con- version state, the SDI input is ignored and may be driven HIGH or LOW. When CS goes LOW and the conversion is complete, SDO goes low and then SDI starts to shift in bits on the rising edge of SCK. Serial Data Output (SDO) The serial data output pin, SDO (Pin 17), provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When CS (Pin 16) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CS = LOW. Chip Select Input (CS) The active LOW chip select, CS (Pin 16), is used to test the conversion status and to enable the data input/output transfer as described in the previous sections. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2439-1 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data input/output state (i.e., after the first rising edge of SCK occurs with CS = LOW). If the device has not finished loading the last input bit (A0 of SDI) by the time CS pulled HIGH, the address information is discarded and the previous ad- dress is kept. APPLICATIO S I FOR ATIO |
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