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LTC2439-1 Datasheet(PDF) 10 Page - Linear Technology |
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LTC2439-1 Datasheet(HTML) 10 Page - Linear Technology |
10 / 28 page LTC2439-1 10 24391f Table 1. Channel Selection MUX ADDRESS CHANNEL SELECTION ODD/ SGL SIGN A2 A1 A0 0 123456789 10 11 12 13 14 15 COM * 000 0 0 IN+ IN– 000 0 1 IN+ IN– 000 1 0 IN+ IN– 000 1 1 IN+ IN– 001 0 0 IN+ IN– 001 0 1 IN+ IN– 001 1 0 IN+ IN– 001 1 1 IN+ IN– 010 0 0 IN– IN+ 010 0 1 IN– IN+ 010 1 0 IN– IN+ 010 1 1 IN– IN+ 011 0 0 IN– IN+ 011 0 1 IN– IN+ 011 1 0 IN– IN+ 011 1 1 IN– IN+ 100 0 0 IN+ IN– 100 0 1 IN+ IN– 100 1 0 IN+ IN– 100 1 1 IN+ IN– 101 0 0 IN+ IN– 101 0 1 IN+ IN– 101 1 0 IN+ IN– 101 1 1 IN+ IN– 110 0 0 IN+ IN– 110 0 1 IN+ IN– 110 1 0 IN+ IN– 110 1 1 IN+ IN– 111 0 0 IN+ IN– 111 0 1 IN+ IN– 111 1 0 IN+ IN– 111 1 1 IN+ IN– *Default at power up APPLICATIO S I FOR ATIO maintain the parasitic capacitance of the connection be- tween these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 10nA input leakage current will develop a 1LBS offset error on an 8k resistor if VREF = 5V. This error has a very strong tempera- ture dependency. |
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