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TMP451JQDQFTQ1 Datasheet(PDF) 5 Page - Texas Instruments |
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TMP451JQDQFTQ1 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 37 page  SCL SDA t (LOW) t R t F t (HDSTA) t (HDSTA) t (HDDAT) t (BUF) t (SUDAT) t (HIGH) t (SUSTA) t (SUSTO) P S S P 5 TMP451-Q1 www.ti.com SLOS877B – OCTOBER 2014 – REVISED JUNE 2019 Product Folder Links: TMP451-Q1 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated Electrical Characteristics (continued) At TA = –40°C to 125°C and V+ = 3.3 V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT DIGITAL OUTPUTS (THERM, ALERT/THERM2) VOL Low-level output voltage IO = 6 mA 0.15 0.4 V IOH High-level output leakage current VO = V+ 1 μA POWER SUPPLY V(V+) Specified voltage range 1.7 3.6 V IQ Quiescent current 0.0625 conversions per second 27 40 μA 16 conversions per second 165 250 μA 32 conversions per second 300 450 μA Serial bus inactive, shutdown mode 3 8 μA Serial bus active, ƒS = 400 kHz, shutdown mode 90 μA Serial bus active, ƒS = 2.5 MHz, shutdown mode 350 μA POR Power-on reset threshold 1.2 1.55 V 6.6 Timing Characteristics for Figure 1 PARAMETER FAST MODE HIGH-SPEED MODE UNIT MIN MAX MIN MAX ƒ(SCL) SCL operating frequency 0.001 0.4 0.001 2.5 MHz t(BUF) Bus free time between STOP and START Condition 1300 260 ns t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns t(SUSTA) Repeated START condition setup time 600 160 ns t(SUSTO) STOP condition setup time 600 160 ns t(HDDAT) Data hold time 0 900 0 150 ns t(SUDAT) Data setup time 100 30 ns t(LOW) SCL clock LOW period 1300 260 ns t(HIGH) SCL clock HIGH period 600 60 ns tF, tR – SDA Data fall and rise time 300 80 ns tF, tR – SCL Clock fall and rise time 300 40 ns tR Rise time for SCL ≤ 100 kHz 1000 ns Figure 1. Two-Wire Timing Diagram |
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