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TL16C750E Datasheet(PDF) 51 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 51 Page - Texas Instruments |
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51 / 59 page  51 TL16C750E www.ti.com SLLSF10 – DECEMBER 2019 Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 10.2.2 Detailed Design Procedure The procedure to setup the part for transmission involves only a few register writes. Each step of the process is outlined 10.2.2.1 Set the desired baud rate As per Table 24, the desired baud rate is 9600 with an input clock of 24 MHz. The math required to calculate the register values is outlined in Programmable Baud Rate Generator with Fractional Divisor and Fractional Divisor. Since the device by default uses a 16x over sample setting, the math is 24E9 / (16 * 9600) = 156.25. This shows that the fractional baud rate feature is required to achieve 9600 baud. Since the fractional baud rate gives x/64 resolution, 0.25 * 64 = 16. The below values are the divisor values to be used in the registers. Table 25. 9600 baud divisor values Register Description Value DLH MSB of the divisor 0x00 DLL LSB of the divisor 0x9C DLF Fractional (1/64) divisor 0x10 Since these registers have access considerations in order to write to them (see Table 8), a few extra writes are required to enable the writes to the desired registers. Table 26. Register writes to configure baud rate Step Description Register & Access Type Value 1 Enable access to EFR (enhanced function) register LCR (0b011) [W] 0xBF 2 Enable the enhanced functionality (fractional baud rate) EFR (0b010) [W] 0x10 3 Enable extra feature registers and 8 bits/no parity/1 stop bit LCR (0b011) [W] 0x93 4 Write the MSB of the divisor DLH (0b001) [W] 0x00 5 Write to the LSB of the divisor DLL (0b000) [W] 0x9C 6 Write to the fractional divisor DLF (0b111) [W] 0x10 7 Change LCR back to normal mode LCR (0b011) [W] 0x13 10.2.2.2 Reset the fifos Since the baud rate and UART settings are configured in the previous section, configuration is complete and the FIFOs are ready to be reset for use. Table 27. Register writes to reset FIFOs Step Description Register & Access Type Value 1 Reset FIFOs FCR (0b010) [W] 0x06 2 Enable the FIFOs FCR (0b010) [W] 0x01 10.2.2.3 Sending data on the bus Once configuration is complete, the part is ready for data transmission. For the example the data 0xAA is written to the bus. This is quite simple to do. Writing to THR (0b000) automatically shifts the written data into an internal FIFO (since FIFOs are enabled) and then begins being shifted out onto the UART bus. Table 28. Register writes to writing data onto the bus Step Description Register & Access Type Value 1 Write data onto bus THR (0b000) [W] 0xAA |
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