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TL16C750E Datasheet(PDF) 47 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 59 page  16 Cycles 16 Cycles 16 Cycles 16 Cycles 16XCLK RX Int_RX Int_TX 16XCLK TX 1 2 3 4 5 6 7 8 12 14 16 10 16XCLK Int_TX TX 16 Cycles 16 Cycles 16 Cycles 16 Cycles Int_TX 16XCLK TX 1 2 3 4 5 6 7 8 12 14 16 10 47 TL16C750E www.ti.com SLLSF10 – DECEMBER 2019 Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated rate is a maximum rate. When both ends of the transfer are setup to a lower but matching speed, the protocol still works. The clock used to code or sample the data is 16 times the baud rate, or 1.843-MHz maximum. To code a 1, no pulse is sent or received for 1-bit time period, or 16 clock cycles. To code a 0, one pulse is sent or received within a 1-bit time period, or 16 clock cycles. The pulse must be at least 1.6-μs wide and 3 clock cycles long at 1.843 MHz. At lower baud rates the pulse can be 1.6 μs wide or as long as 3 clock cycles. The transmitter output, TX, is intended to drive a LED circuit to generate an infrared pulse. The LED circuits work on positive pulses. A terminal circuit is expected to create the receiver input, RX. Most, but not all, PIN circuits have inversion and generate negative pulses from the detected infrared light. Their output is normally high. The TL16C750E device can decode either negative or positive pulses on RX. 9.5.19 IrDA Encoder Function Serial data from a UART is encoded to transmit data to the optoelectronics. While the serial data input to this block (Int_TX) is high, the output (TX) is always low, and the counter used to form a pulse on TX is continuously cleared. After Int_TX resets to 0, TX rises on the falling edge of the 7th 16XCLK. On the falling edge of the 10th 16XCLK pulse, TX falls, creating a 3-clock-wide pulse. While Int_TX stays low, a pulse is transmitted during the seventh to tenth clocks of each 16-clock bit cycle. Figure 35. IrDA-SIR Encoding Scheme – Detailed Timing Diagram Figure 36. Encoding Scheme – Macro View After reset, Int_RX is high and the 4-bit counter is cleared. When a falling edge is detected on RX, Int_RX falls on the next rising edge of 16XCLK with sufficient setup time. Int_RX stays low for 16 cycles (16XCLK) and then returns to high as required by the IrDA specification. As long as no pulses (falling edges) are detected on RX, Int_RX remains high. Figure 37. IrDA-SIR Decoding Scheme – Detailed Timing Diagram Figure 38. IrDA-SIR Decoding Scheme – Macro View It is possible for jitter or slight frequency differences to cause the next falling edge on RX to be missed for one 16XCLK cycle. In that case, a 1-clock-wide pulse appears on Int_RX between consecutive 0s. It is important for the UART to strobe Int_RX in the middle of the bit time to avoid latching this 1-clock-wide pulse. The TL16C750E UART already strobes incoming serial data at the proper time. Otherwise, note that data is required to be framed by a leading 0 and a trailing 1. The falling edge of that first 0 on Int_RX synchronizes the read strobe. The strobe occurs on the 8th 16XCLK pulse after the Int_RX falling edge and once every 16 cycles thereafter until the stop bit occurs. |
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