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TL16C750E Datasheet(PDF) 45 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 45 Page - Texas Instruments |
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45 / 59 page  WR THR TX DTRx 1 Baud Time Controlled by DLY[2:0] 45 TL16C750E www.ti.com SLLSF10 – DECEMBER 2019 Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table 23. LOOP and RCVEN Functionality LOOP MODE RCVEN AFR MODE DESCRIPTION LOOP mode off, MCR4 = 0, RX, TX active RCVEN = 1 AFR = 10 RS-232 Receive threshold, timeout, and error detection interrupts available Data stored in receive FIFO AFR = 14 RS-485 Receive threshold, timeout, and error detection interrupts available Data stored in receive FIFO AFR = 12 IrDA Receive threshold, timeout, and error detection interrupts available Data stored in receive FIFO RCVEN = 0 AFR = 00 RS-232 Receive threshold and error detection interrupts available Data stored in receive FIFO AFR = 04 RS-485 No data stored in receive FIFO, hence no interrupts available AFR = 02 IrDA No data stored in receive FIFO, hence no interrupts available LOOP mode on, MCR4 = 1, RX, TX inactive RCVEN = 1 AFR = 10 RS-232 Receive threshold, timeout, and error detection interrupts available Data stored in receive FIFO AFR = 14 RS-485 Receive threshold, timeout, and error detection interrupts available Data stored in receive FIFO AFR = 12 IrDA Receive threshold, timeout, and error detection interrupts available Data stored in receive FIFO RCVEN = 0 AFR = 00 RS-232 Receive threshold and error detection interrupts available Data stored in receive FIFO AFR = 04 RS-485 Receive threshold and error detection interrupts available Data stored in receive FIFO AFR = 02 IrDA Receive threshold and error detection interrupts available Data stored in receive FIFO 9.5.17 RS-485 Mode The RS-485 mode is intended to simplify the interface between the UART and an RS-485 driver or transceiver. When enabled by setting 485EN, the DTR output goes high one bit time before the first stop bit of the first data byte being sent, and remains high as long as there is pending data in the TSR or THR (xmt fifo). After both are empty (after the last stop bit of the last data byte), the DTR output stays high for a programmable delay of 0 to 15 bit times, as set by DLY[2:0]. This helps preserve data integrity over long signal lines. This is illustrated in the following. Often RS-485 packets are relatively short and the entire packet can fit within the 128 byte xmt fifo. In this case, it goes empty when the TSR goes empty. But in cases where a larger block needs to be sent, it is advantageous to reload the xmt fifo as soon as it is depleted. Otherwise, the transmission stalls while waiting for the xmt fifo to be reloaded, which varies with processor load. In this case, it is best to also set 485LG (large block), which causes the transmit interrupt to occur wither when the THR becomes empty (if the xmt fifo level was not above the threshold), or when the xmt fifo threshold is crossed. The reloading of the xmt fifo occurs while some data is being shifted out, eliminating fifo underrun. If desired, when the last bytes of a current transmission are being loaded in the xmt fifo, 485LG can be cleared before the load and the transmit interrupt occurs on the TSR going empty. A. Waveforms are not shown to scale, as the WR THR pulses typically are less than 100 ns, where the TX waveform varies with baud rate but is typically in the microsecond range. Figure 31. DTRx and Transmit Data Relationship |
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