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TL16C750E Datasheet(PDF) 44 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 44 Page - Texas Instruments |
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44 / 59 page  44 TL16C750E SLLSF10 – DECEMBER 2019 www.ti.com Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 9.5.15 FIFO Ready Register The FIFO ready register provides realtime status of the transmit and receive FIFOs. Table 21 shows the FIFO ready register bit settings. The trigger level mentioned in Table 21 refers to the setting in either FCR (when TLR value is 0), or TLR (when it has a nonzero value). Table 21. FIFO Ready Register BIT BIT SETTINGS 0 0 = There are fewer than a TX trigger level number of spaces available in the TX FIFO. 1 = There are at least a TX trigger level number of spaces available in the TX FIFO. 3:1 Unused, always 0. 4 0 = There are fewer than a RX trigger level number of characters in the RX FIFO. 1 = The RX FIFO has more than a RX trigger level number of characters available for reading or a timeout condition has occurred. 7:5 Unused, always 0 The FIFORdy register is a read only register and can be accessed when the UART is selected. CS = 0, MCR[2] (FIFORdy Enable) is a logic 1, and loopback is disabled. Its address is 111. 9.5.16 Alternate Function Register (AFR) The AFR is used to enable some extra functionality beyond the capabilities of the original TL16C750. The first addition is the IrDA mode, which supports Standard IrDA (SIR) mode with baud rates from 2400 to 115.2 kbps. The third addition is support for RS-485 bus drivers or transceivers by providing an output pin (DTR), which is timed to keep the RS-485 driver enabled as long as transmit data is pending. The AFR is located at A[2:0] = 010 when LCR[7:5] = 100. Table 22. AFR Bit Settings BIT BIT SETTINGS 0 Reserved bit. Does not do anything 1 IREN enables the IrDA SIR mode. This mode is only specified to 115.2 bps; TI does not recommend the use of this mode at higher speeds. 2 485EN enables the half duplex RS-485 mode and causes the DTR output to be set high whenever there is any data in the THR or TSR and to be held high until the delay set by DLY2:0 has expired, at which time it is set low. The DTR output is intended to drive the enabled input of an RS-485 driver. When this bit is set, the transmitter interrupts are held off until the TSR is empty, unless 485LG is set. 3 485LG is set when the 485EN is set. This bit indicates that a relatively large data block is being set, requiring more than a single load of the xmt fifo. In this case, the transmitter interrupts occur as in the standard RS-232 mode, either when the xmt fifo contents drop below the xmt threshold or when the xmt fifo is empty. 4 RCVEN is valid only when 485EN or IREN is set, and allows the serial receiver to listen in or snoop on the RS-485 traffic or IrDA traffic. RS-485 mode is generally considered half duplex, and usually a node is either driving or receiving, but there can be cases when it is advantageous to verify what you are sending. This can be used to detect collisions or as part of an arbitration mechanism on the bus. When both RCVEN and 485EN are set, the receiver stores any data presented on RX, if any. Note that implies that the external RS-485 receiver is enabled. Whenever 485EN is cleared, the serial receiver is enabled for normal full duplex RS-232 traffic. If RCVEN is cleared while 485EN is set, the receiver is disabled while transmitting. SIR is also considered half duplex. Often the light energy from the transmitting LED is coupled back into the receiving PIN diode, which creates an input data stream that is not of interest to the host. Disabling the receiver (clearing RCVEN) prevents this reception, and eliminates the task of unloading the data. On the other hand, for diagnostic or other purposes, it may be useful to observe this data stream. For example, a mirror could be used to intentionally couple the output LED to the input PIN. For these cases, RCVEN could be set to enable the receiver. NOTE: When RCVEN is cleared (set to 0), the character timeout interrupt is not available, even in RS-232 mode. This can be useful when checking code for valid threshold interrupts, as the timeout interrupt does not override the threshold interrupt. 7:5 DLY2 to DLY0 sets a delay after the last stop bit of the last data byte being set before the DTR is set low, to allow for long cable runs. The delay is in number of bit times and is enabled by 485EN. The delay starts only when both the xmt serial shift register (TSR) is empty and the xmt fifo (THR) is empty, and if started, is cleared by any data being written to the THR. |
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