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TL16C750E Datasheet(PDF) 43 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 59 page  43 TL16C750E www.ti.com SLLSF10 – DECEMBER 2019 Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 9.5.12 Divisor Latches (DLL, DLH, DLF) Two 8-bit registers store the 16-bit divisor and a 6-bit fractional divisor for generation of the baud clock in the baud rate generator. DLH, stores the most significant part of the divisor. DLL stores the least significant part of the division. DLF stores the fractional value of the divisor as x / 64 where x is the value in DLF. Table 18. DLF Bit Values BIT BIT SETTINGS 7 Baud divider bit 0 (default) = Enable divide-by-16 baud divider 1 = Enable divide-by-8 baud divider 6 Reserved 5:0 6 bit fractional divider value (x / 64) For more information on how to calculate the fractional values, see Fractional Divisor. DLL, DLH and DLF can only be written to before sleep mode is enabled (that is, before IER[4] is set). 9.5.13 Transmission Control Register (TCR) This 8-bit register is used to store the receive FIFO threshold levels to start or stop transmission during hardware or software flow control. Table 19 shows transmission control register bit settings. Table 19. TCR Bit Settings BIT BIT SETTINGS 3:0 RCV FIFO trigger level to HALT transmission (0 to 60) 7:4 RCV FIFO trigger level to RESTORE transmission (0 to 60) TCR trigger levels are available from 0 to 120 bytes with a granularity of 8. TCR can be written to only when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious operation of the device. 9.5.14 Trigger Level Register (TLR) This 8-bit register is used to store the transmit and received FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 8 to 120 can be programmed with a granularity of 8. Table 20 shows trigger level register bit settings. Table 20. TLR Bit Settings BIT BIT SETTINGS 3:0 Transmit FIFO trigger levels (8 to 120), number of spaces available 7:4 RCV FIFO trigger levels (8 to 120), number of characters available TLR can be written to only when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are 0, then the selectable trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger levels. Trigger levels from 8 to 120 bytes are available with a granularity of 8. The TLR should be programmed for N / 8, where N is the desired trigger level. |
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